MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

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3.3V PLL Clock Driver

The MPC974 is a fully integrated PLL based clock generator and clock

distribution chip which operates from a 3.3V supply. The MPC974 is

ideally suited for high speed, timing critical designs which need a high

level of clock fanout. The device features 15 high drive LVCMOS outputs,

each output has the capability of driving a 50

Ω parallel terminated

transmission line or two 50

Ω series terminated transmission lines on the

incident edge.

The MPC974 features 3 independent frequency programmable banks

of outputs. The frequency programmability offers the capability of

establishing output frequency relationships of 1:1, 2:1, 3:1, 3:2 and 3:2:1.

In addition, the device features a separate feedback output which allows

for a wide variety of input/output frequency multiplication alternatives.

The VCO_Sel pin provides an extended VCO lock range for added

flexibility and general purpose usage.

The TCLK0 and TCLK1 inputs provide a method for dynamically

switching the PLL between two different clock sources. The PLL has been

optimized to provide small deviations in output pulse width and well

controlled, slow transition back to lock when the inputs are switched

between two references that are equal in frequency but out of phase with

each other. This feature makes the MPC974 an ideal solution for fault

tolerant applications which require redundant clock sources.

All of the control pins are LVTTL/LVCMOS level inputs. The Fsel pins control the VCO divide ratios that are applied to the

various output banks and the feedback output. The MR input will reset the internal flip flops and place the outputs in high

impedance when driven LOW. The OE pin will force all of the outputs except the feedback output LOW to allow for acquiring

phase lock prior to providing clocks to the rest of the system. Note that the OE pin is not synchronized to the internal clock. As a

result, the initial pulse after de–assertion of the OE pin may be distorted. The PLL_En pin allows the PLL to be bypassed for

board level functional test. When bypassed the signal on the selected TCLK will be routed around the PLL and will drive the

internal dividers directly.

The MPC974 is packaged in the 52–lead TQFP package to provide optimum electrical performance as well as minimize board

space requirements. The device is specified for 3.3V VCC.

MPC974

LOW VOLTAGE

PLL CLOCK DRIVER

FA SUFFIX

52–LEAD TQFP PACKAGE

CASE 848D-03