AD7705 datasheet(21/44 Pages) AD

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AD7705/AD7706

Rev. C | Page 21 of 44

CIRCUIT DESCRIPTION

The AD7705/AD7706 are Σ-Δ analog-to-digital converters (ADC)

with on-chip digital filtering, intended for the measurement of

wide, dynamic range, low frequency signals, such as those in

industrial-control or process-control applications. Each contains

a Σ-Δ (or charge-balancing) ADC, a calibration microcontroller

with on-chip static RAM, a clock oscillator, a digital filter, and a

bidirectional serial communication port. The parts consume only

320 μA of power supply current, making them ideal for battery-

powered or loop-powered instruments. These parts operate with

a supply voltage of 2.7 V to 3.3 V or 4.75 V to 5.25 V.

The AD7705 contains two programmable-gain, fully differential

analog input channels, and the AD7706 contains three pseudo

differential analog input channels. The selectable gains on these

inputs are 1, 2, 4, 8, 16, 32, 64, and 128, allowing the parts to accept

unipolar signals of 0 mV to 20 mV and 0 V to 2.5 V, or bipolar

signals in the range of ±20 mV to ±2.5 V when the reference input

voltage equals 2.5 V. With a reference voltage of 1.225 V, the input

ranges are from 0 mV to 10 mV and 0 V to 1.225 V in unipolar

mode, and from ±10 mV to ±1.225 V in bipolar mode. Note that

the bipolar ranges are with respect to AIN(−) on the AD7705,

and with respect to COMMON on the AD7706, but not with

respect to GND.

The input signal to the analog input is continuously sampled at a

rate determined by the frequency of the master clock, MCLK IN,

and the selected gain. A charge-balancing ADC (∑-Δ modulator)

converts the sampled signal into a digital pulse train whose duty

cycle contains the digital information. The programmable gain

function on the analog input is also incorporated in this Σ-Δ

modulator, with the input sampling frequency being modified

to provide higher gains. A sinc3, digital, low-pass filter processes

the output of the Σ-Δ modulator and updates the output register

at a rate determined by the first notch frequency of this filter.

The output data can be read from the serial port randomly or

periodically at any rate up to the output register update rate.

The frequency of the first notch of the digital filter ranges from

50 Hz to 500 Hz; therefore, the programmable range for the

−3 dB frequency is 13.1 Hz to 131 Hz. With a master clock

frequency of 1 MHz, the programmable range for this first

notch frequency is 20 Hz to 200 Hz, giving a programmable

range for the −3 dB frequency of 5.24 Hz to 52.4 Hz.

The AD7705 basic connection diagram is shown in Figure 13.

It shows the AD7705 driven from an analog 5 V supply. An

AD780 or REF192 precision 2.5 V reference provides the reference

source for the part. On the digital side, the part is configured for

3-wire operation with CS tied to GND. A quartz crystal or ceramic

resonator provides the master clock source for the part. In most

cases, it is necessary to connect capacitors on the crystal or

resonator to ensure that it does not oscillate at overtones of its

fundamental operating frequency. The values of capacitors vary,

depending on the manufacturer’s specifications. The same setup

applies to the AD7706.

VDD

ANALOG

5V SUPPLY

μF

AIN1(+)

AIN1(–)

AIN2(+)

AIN2(–)

DIFFERENTIAL

ANALOG

INPUT

DIFFERENTIAL

ANALOG

INPUT

GND

REF IN(+)

REF IN(–)

μF

VIN

ANALOG 5V

SUPPLY

AD780/

REF192

VOUT

GND

AD7705

DRDY

DATA READY

DOUT

RECEIVE (READ)

DIN

SERIAL DATA

SCLK

SERIAL CLOCK

RESET

MCLK IN

MCLK OUT

CRYSTAL OR

CERAMIC

RESONATOR

0.1

μF

0.1

μF

Figure 13. AD7705 Basic Connection Diagram

AD7705 Datasheet(PDF) 21 Page - Analog Devices

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