THS1030

3V TO 5.5V, 10BIT, 30 MSPS

CMOS ANALOGTODIGITAL CONVERTER

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

21

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

onboard reference generator configuration (continued)

_

+

VBG

Internal

Reference

Buffer

REFSENSE

AGND

VREF = External

AVDD

_

+

Mode =

AVDD

2

Figure 23. Drive VREF Mode

operating configuration examples

This section provides examples of operating configurations.

Figure 24 shows the operating configuration in top/bottom mode for a 2-V span single-ended input, using VREF

REFSENSE to AGND sets the output of the ORG to 2 V. REFTS and REFBS are user-connected to VREF and

AGND respectively to match the AIN pin input range to the voltage range of the input signal.

AIN

REFTF

REFBF

REFSENSE

MODE

AVDD

2 V

0 V

0.1

µF

10

µF

0.1

µF

0.1

µF

1 V

VREF = 2 V

REFTS

REFBS

Figure 24. Operation Configuration in Top/Bottom Mode

to be applied to REFTS and REFBS. The differential input goes from −0.8 V to 0.8 V, giving a total input signal

span of 1.6 V, REFTF− REFBF should therefore equal 1.6 V. REFSENSE is connected to resistors RA and RB