THS1030CPWR datasheet(12/39 Pages) TI1

12 / 39 page

THS1030

3V TO 5.5V, 10BIT, 30 MSPS

CMOS ANALOGTODIGITAL CONVERTER

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

The analog input AIN is sampled in the sample and hold unit, the output of which feeds the ADC core, where

the process of analog to digital conversion is performed against ADC reference voltages, REFTF and REFBF.

Connecting the MODE pin to one of three voltages, AGND, AVDD or AVDD/2 sets up operating configurations.

The three settings open or close internal switches to select one of the three basic methods of ADC reference

generation.

Depending on the user’s choice of operating configuration, the ADC reference voltages may come from the

internal reference buffer or may be fed from completely external sources. Where the reference buffer is

employed, the user can choose to drive it from the onboard reference generator (ORG), or may use an external

voltage source. A specific configuration is selected by connections to the REFSENSE, VREF, REFTS and

REFBS, and REFTF and REFBF pins, along with any external voltage sources selected by the user.

The ADC core drives out through output buffers to the data pins D0 to D9. The output buffers can be disabled

by the OE pin.

A single, sample-rate clock (30 MHz maximum) is required at pin CLK. The analog input signal is sampled on

the rising edge of CLK, and corresponding data is output after following third rising edge.

The STBY pin controls the THS1030 power down.

The user-chosen operating configuration and reference voltages determine what input signal voltage range the

THS1030 can handle.

The following sections explain:

D The internal signal flow of the device, and how the input signal span is related to the ADC reference voltages

D The ways in which the ADC reference voltages can be buffered internally, or externally applied

D How to set the onboard reference generator output, if required, and several examples of complete

configurations

signal processing chain (sample and hold, ADC)

Figure 11 shows the signal flow through the sample and hold unit to the ADC core.

Sample

and

Hold

−1/2

ADC

Core

VP+

VP−

REFTF

REFBF

AIN

REFTS

REFBS

Figure 11. Analog Input Signal Flow

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