THS1030CPWR datasheet(29/39 Pages) TI1

29 / 39 page

THS1030

3V TO 5.5V, 10BIT, 30 MSPS

CMOS ANALOGTODIGITAL CONVERTER

SLAS243E − NOVEMBER 1999 − REVISED DECEMBER 2003

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

user tips for obtaining best performance from the THS1030

D Voltages on AIN, REFTF and REFBF and REFTS and REFBS must all be inside the supply rails.

D ORG modes offer the simplest configurations for ADC reference generation.

D Choose differential input mode for best distortion performance.

D Choose a 2-V ADC input span for best noise performance.

D Choose a 1-V ADC input span for best distortion performance.

D If the ORG is not used to provide ADC reference voltages, its output may be used for other purposes in the

system. Care should be taken to ensure noise is not injected into the THS1030.

D Use external voltage sources for ADC reference generation where there are stringent requirements on

accuracy and drift.

D Drive clock input CLK from a low-jitter, fast logic stage, with a well-decoupled power supply and short PCB

traces.

TLC876 mode

The THS1030 is pin compatible with the TI TLC876 and thus enables users of TLC876 to upgrade to higher

speed by dropping the THS1030 into their sockets. Grounding the 1876M pin effectively puts the THS1030 into

876 mode using the external ADC reference. The MODE pin should either be grounded or left floating.

The REFSENSE pin is connected to DVDD when the THS1030 is dropped into a TLC876 socket. For

DVDD = 5-V applications, this will disable the ORG. For TLC876 applications using DVDD = 3.3 V, the VREF pin

will be driven to AVSS. In TLC876/AD876 mode, the pipeline latency is increased to 3.5 clock cycles to match

the TLC876 latency.

THS1030CPWR Datasheet(PDF) 29 Page - Texas Instruments