CY3663 datasheet(49/92 Pages) CYPRESS

49 / 92 page

CY7C67200

Document Number: 38-08014 Rev. *I

Page 49 of 92

Transmit Ready (Bit 4)

The Transmit Ready bit is a read only bit that indicates if the HSS

Transmit FIFO is ready for the CPU to load new data for trans-

mission.

1: HSS transmit FIFO ready for loading

0: HSS transmit FIFO not ready for loading

Packet Mode Select (Bit 3)

The Packet Mode Select bit selects between Receive Packet

Ready and Receive Ready as the interrupt source for the RxIntr

interrupt.

1: Selects Receive Packet Ready as the source

0: Selects Receive Ready as the source

Receive Overflow Flag (Bit 2)

The Receive Overflow Flag bit indicates if the Receive FIFO

overflowed when set. This flag can be cleared by writing a ‘1’ to

this bit.

1: Overflow occurred

0: Overflow did not occur

Receive Packet Ready Flag (Bit 1)

The Receive Packet Ready Flag bit is a read only bit that

indicates if the HSS receive FIFO is full with eight bytes.

1: HSS receive FIFO is full

0: HSS receive FIFO is not full

Receive Ready Flag (Bit 0)

The Receive Ready Flag is a read only bit that indicates if the

HSS receive FIFO is empty.

1: HSS receive FIFO is not empty (one or more bytes is reading

for reading)

0: HSS receive FIFO is empty

HSS Baud Rate Register [0xC072] [R/W]

Figure 49. HSS Baud Rate Register

Bit #

Field

Reserved

Baud...

Read/Write

R/W

Default

Bit #

Field

...Baud

Read/Write

R/W

Default

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