CY3663 datasheet(28/92 Pages) CYPRESS

28 / 92 page

CY7C67200

Document Number: 38-08014 Rev. *I

Page 28 of 92

1: Enable SOF/EOP timer interrupt

0: Disable SOF/EOP timer interrupt

Port A Wake Interrupt Enable (Bit 6)

The Port A Wake Interrupt Enable bit enables or disables the

remote wakeup interrupt for Port A.

1: Enable remote wakeup interrupt for Port A

0: Disable remote wakeup interrupt for Port A

Port A Connect Change Interrupt Enable (Bit 4)

The Port A Connect Change Interrupt Enable bit enables or

disables the Connect Change interrupt on Port A. This interrupt

triggers when either a device is inserted (SE0 state to J state) or

a device is removed (J state to SE0 state).

1: Enable Connect Change interrupt

0: Disable Connect Change interrupt

Done Interrupt Enable (Bit 0)

The Done Interrupt Enable bit enables or disables the USB

Transfer Done interrupt. The USB Transfer Done triggers when

either the host responds with an ACK, or a device responds with

any of the following: ACK, NAK, STALL, or Timeout. This

interrupt is used for both Port A and Port B.

1: Enable USB Transfer Done interrupt

0: Disable USB Transfer Done interrupt

Reserved

All reserved bits must be written as ‘0’.

Host n Status Register [R/W]

■ Host 1 Status Register 0xC090

■ Host 2 Status Register 0xC0B0

Figure 26. Host n Status Register

The Host n Status register provides status information for host

operation. Pending interrupts can be cleared by writing a ‘1’ to

the corresponding bit. This register can be accessed by the HPI

interface.

VBUS Interrupt Flag (Bit 15)

The VBUS Interrupt Flag bit indicates the status of the OTG

VBUS interrupt (only for Port 1A). When enabled this interrupt

triggers on both the rising and falling edge of VBUS at 4.4 V. This

bit is only available for Host 1 and is a reserved bit in Host 2.

1: Interrupt triggered

0: Interrupt did not trigger

ID Interrupt Flag (Bit 14)

The ID Interrupt Flag bit indicates the status of the OTG ID

interrupt (only for Port 1A). When enabled this interrupt triggers

on both the rising and falling edge of the OTG ID pin. This bit is

only available for Host 1 and is a reserved bit in Host 2.

1: Interrupt triggered

0: Interrupt did not trigger

SOF/EOP Interrupt Flag (Bit 9)

The SOF/EOP Interrupt Flag bit indicates the status of the

SOF/EOP Timer interrupt. This bit triggers ‘1’ when the

SOF/EOP timer expires.

1: Interrupt triggered

0: Interrupt did not trigger

Bit #

Field

VBUS

Interrupt Flag

ID Interrupt

Flag

Reserved

SOF/EOP

Interrupt Flag

Reserved

Read/Write

R/W

Default

Bit #

Field

Reserved

Port A

Wake Interrupt

Flag

Reserved

Port A Connect

Change

Interrupt Flag

Reserved

Port A

SE0

Status

Reserved

Done

Interrupt Flag

Read/Write

R/W

Default

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