Errata

Specification Update

13

Errata

1.

Audio Noise With High LPC Traffic

Problem:

Audio under-run during high LPC traffic

Implication:

Momentary audio streaming interruption

Workaround:

None. LPC utilization is fairly low after BIOS has been shadowed and should not affect

audio play back.

Status:

For the steppings affected, see the Summary Tables of Changes.

2.

System Hang With PCIe Upstream Memory Write To FEE00000 With

No Data

Problem:

When a PCI Express device initiates a FEE00000 write with all byte enable disabled, the

Intel SCH turns it into an MSI write, but the Intel SCH continues to wait for a data

payload that does not exist.

Implication:

System may hang. This is a PCI Express compliance violation.

Workaround:

None. Downstream devices should not initiate these types of transactions.

Status:

For the steppings affected, see the Summary Tables of Changes.

3.

PCIe PLL May Not Power Down In L1 State

Problem:

Power management logic (in the PCIe unit) fails to power down the PLL when one of the

PCIe ports is in function disable and the other port is in the L1 state.

Implication:

A potential loss of ~100 mW in power savings if one of the PCIe ports is in function

disable.

Workaround:

None

Status:

For the steppings affected, see the Summary Tables of Changes.

4.

EHCI Controller—Unable To Mask Wake Events Per Port

Problem:

The Controller cannot mask any ports against EHCI wake events.

Implication:

Any EHCI port can cause system to wake

Workaround:

None

Status:

For the steppings affected, see the Summary Tables of Changes.

5.

PCIe Controller Fails To Go Into L1 State In Some Configurations

Problem:

If PCIe port 1 is populated and PCIe port 0 is not populated, both PCIe ports fail to go

into L1 state to reduce power.

Implication:

Fails to recognize an estimated power saving of approximate 100 mW

Workaround:

If only one PCIe port is needed in a design, use Port 0 and function disable Port 1. If

two PCIe ports exist on the platform, use port 0 first.

Status:

For the steppings affected, see the Summary Tables of Changes.