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82US15W Datasheet(PDF) 14 Page - Intel Corporation

Part # 82US15W
Description  Intel짰 System Controller Hub
PDF  22 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82US15W Datasheet(HTML) 14 Page - Intel Corporation

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Errata
14
Specification Update
6.
High Definition Audio Does Not Send Interrupts to the CPU When
Using the MSI
Problem:
The HDA unit cannot send interrupts to the CPU when using the MSI.
Implication:
OS or media applications will revert to the legacy method to send interrupts.
Workaround:
None
Status:
For the steppings affected, see the Summary Tables of Changes.
7.
Incorrect TPM Access
Problem:
A host byte read access to the TPM mo dule (by me ans of the LPC bus) causes four
single byte reads on LPC instead of a single byte read.
Implication:
The TPM module uses a FIFO which after the first host byte 0 read, is incremented to
provide byte 4 upon the next host byte read due the behavior of the Intel SCH.
Software is actually expecting TPM byte 1 t o be read upon the second transaction.
Third party software stacks will not properly function due to this erratum.
Workaround:
None
Status:
For the steppings affected, see the Summary Tables of Changes.
8.
LPC Prefetch Outside of FWH Region
Problem:
The Intel SCH has a feature called FWH prefetching and this allows for a 64-byte fetch
of the FWH device sitting on the LPC bus. This prefetch option is supposed to be
confined to only the address range of the FWH. However, unintentional prefetching may
also extend to other addresses.
Implication:
Some devices such as TPM modules will return incorrect data because these devices do
not allow prefetching.
Workaround:
Disable BIOS prefetching by setting D31:F0, offset D8h, bit 8 = 0. Overall boot time
may increase. This workaround is only required when using devices that do not allow
prefetching (such as TPM modules).
Status:
For the steppings affected, see the Summary Tables of Changes.
9.
PATA Maximum Slew Rate Specification Violation
Problem:
The PATA output buffers for the Intel SCH may violate the ATA maximum slew rate
specification of 1. 0 V/ns under fast corner conditions. No vi olations of Voh/Vol,
overshoot or undershoot have been observed.
Implication:
This is a specification violation using synthetic load testing only. No functional failures
have been observed.
Workaround:
None
Status:
For the steppings affected, see the Summary Tables of Changes.
10.
USB Client Drops Data—Which Causes CRC Errors in Full-Speed Mode
Problem:
CRC errors in customer systems may lower USB performance or cause the connected
USB 1.1 host system to disable a USB-client and signal error to end-user. The last byte
of a USB packet may be lost and this causes the USB client to detect a CRC error.
Implication:
Impact is part dependent and limited to when the client is connected with USB 1.1
hosts only. Some affected parts may have no noticeable impact. CRC errors may cause
a port to be reset and retried, but if errors continue and the port is reset three times,
the host operating system will disable the client device and flag an error message.
Workaround:
Use USB 2.0 host only with the current USB Client driver to continue USB Client
application development and validation. The PV USB Client driver will have an
infrastructure that the OEM user-mode application can use to take the appropriate
action if the client is connected to a full-speed host.



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