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82US15W Datasheet(PDF) 4 Page - Intel Corporation |
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82US15W Datasheet(HTML) 4 Page - Intel Corporation |
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4 / 22 page ![]() 4 Specification Update Revision History § § Revision Number Description Revision Date -001 Initial release April 2008 -002 Added Errata 12 - 17 Specification Changes: Added support for 2 GB DRAM and 2 Gb devices; changed supported MMC specification to 4.1; updated CLKREQ# and SMB_ALERT# behavior Specification Clarifications: Corrected PMBL register default value; added RTC_Xn input DC Specifications July 2008 -003 Added Erratum 18 August 2008 -004 Added Errata 19 - 20 Added New Stepping Identification Information September 2008 -005 Specification Clarifications: Added note to RTCRST# pin description November 2008 -006 Added Errata 21 - 22 Specification Clarifications: Definition of SDIO bit PSTATE.WP; Non-Snoop Cycles December 2008 -007 Specification Clarifications: Correction of LVDS output levels in Reset, Post-Reset; Correction of UHCI Resume Enable Register March 2009 -008 Added Erratum 23 Specification Clarifications: Removed WAKEEN; corrected Resume well GPIO defaults; clarified other registers in the Resume well Documentation Changes: Removed USB Legacy Keyboard Operation June 2009 -009 Added information for US15X SKU May 2010 -010 Added Errata 24 - 26 Specification Clarification: Correction to definition of SDIO bit PSTATE.CSS July 2011 |
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