Errata

18

Specification Update

24.

PCI Express* Unaligned Memory Read Data Corruption

Problem:

The Byte Enable (BE) field in a PCI Express* (PCIe*) transaction is invalid when an

unaligned memory read transaction is performed on the PCIe* memory mapped I/O

(MMIO) device space. F or reads that cross the DWORD boundary, the first BE field

incorrectly matches the last BE field instead of being the complement for a proper data

read (e.g., BE fields for a four byte read results in 0011b and 0011b instead of 0011b

and 1100b.)

Implication:

Reads from the MMIO space that crosses the DWORD boundary causes data corruption.

Workaround:

None.

Status:

For the steppings affected, see the Summary Tables of Changes.

25.

USB Client High Speed Termination Delay

Problem:

Intel® SCH as a USB client waits to disconnect the D+ pull-up resistor until the host

stops transmitting the Chirp JKJKJK sequence to identify the client as a high speed USB

device.

Implication:

Potential violation of USB 2.0 Client Specification, as the USB client should disconnect

the D+ pull-up resistor and send back a Chirp K within 500 uSec of receiving the Chirp

JKJKJK sequence from the USB host.

Workaround:

None. USB 2.0 compliance may be obtained via waiver given that validation of behavior

does not impact host recognition of high speed USB client.

Status:

For the steppings affected, see the Summary Tables of Changes.

26.

USB Audio Device Underrun/Overrun

Problem:

During the transition from C3 or C4 state to C2 (C2 pop-up time), USB classic mode

can lead to underrun/overrun situation while performing an isochronous transaction

(e.g., video/audio streaming).

Implication:

Platforms requiring isochronous transactions on USB classic mode could show transient

transfer errors.

Workaround:

None. Adjust the MTH register to lengthen the wait time entering C3/C4 state, or

attach the device through a USB 2.0 hub to Intel® SCH.

Status:

For the steppings affected, see the Summary Tables of Changes.