100:

100 pF

Output

Snubber

Network

LM7301

V

+

OUT

V

-

-

+

LM7301

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SNOS879H – AUGUST 1999 – REVISED MARCH 2013

STABILITY CONSIDERATIONS

Rail-to-rail output amplifiers like the LM7301 use the collector of the drive transistor(s) at the output pin, as

shown in Figure 29. This allows the load to be driven as close as possible towards either supply rail.

Figure 29. Simplified Output Stage Block Diagram

While this architecture maximizes the load voltage swing range, it increases the dependence of loop gain and

subsequently stability, on load impedance and DC load current, compared to a non-rail-to-rail architecture. Thus,

with this type of output stage, it is even more crucial to ensure stability by meticulous bench verification under all

load conditions, and to apply the necessary compensation or circuit modifications to overcome any instability, if

necessary. Any such bench verification should also include temperature, supply voltage, input common mode

and output bias point variations as well as capacitive loading.

For example, one set of conditions for which stability of the LM7301 amplifier may be compromised is when the

DC output load is larger than +/-0.5 mA, with input and output biased to mid-rail. Under such conditions, it may

be possible to observe open-loop gain response peaking at a high frequency (e.g. 200 MHz), which is beyond

the expected frequency range of the LM7301 (4 MHz GBW). Without taking any precautions against gain

peaking, it is possible to see increased settling time or even oscillations, especially with low closed loop gain and

/ or light AC loading. It is possible to reduce or eliminate this gain peaking by using external compensation

components. One possible scheme that can be applied to reduce or eliminate this gain peaking is shown in

Figure 30.

Figure 30. Non-dissipating Snubber Network to Reduce Gain Peaking

with no DC loading so that total power dissipation is not increased. The increased AC load effectively reduces

loop gain at higher frequencies thereby reducing gain peaking due to the possible causes stated above. For the

case peaking conditions (I_source= 2mA DC @ around 180MHz) thus confining loop gain below 0dB and

particular application to take into account other subtleties and tolerances.

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