EVAL-AD5063EB datasheet(5/20 Pages) AD

Part #	EVAL-AD5063EB

Description	Fully Accurate 16-Bit VOUT nanoDAC SPI Interface 2.7 V to 5.5 V in an MSOP

PDF	20 Pages

Scroll/Zoom	100%

Manufacturer	AD [Analog Devices]

Direct Link	http://www.analog.com

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5 / 20 page

AD5063

Rev. C | Page 5 of

TIMING CHARACTERISTICS

VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.

Table 3.

Parameter

Limit1

Unit

Test Conditions/Comments

t12

ns min

SCLK cycle time

ns min

SCLK high time

ns min

SCLK low time

ns min

SYNC to SCLK falling edge setup time

ns min

Data setup time

ns min

Data hold time

ns min

SCLK falling edge to SYNC rising edge

ns min

Minimum SYNC high time

ns min

SYNC rising edge to next SCLK fall ignore

1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

2 Maximum SCLK frequency is 30 MHz.

D22

D23

SYNC

SCLK

D23

D22

DIN

Figure 2. Timing Diagram

EVAL-AD5063EB Datasheet(PDF) 5 Page - Analog Devices