EVAL-AD5063EB datasheet(13/20 Pages) AD

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AD5063

Rev. C | Page 13 of

THEORY OF OPERATION

The AD5063 is a single 16-bit, serial input, voltage-output DAC.

It operates from supply voltages of 2.7 V to 5.5 V. Data is

written to the AD5063 in a 24-bit word format via a 3-wire serial

interface.

The AD5063 incorporates a power-on reset circuit that ensures

the DAC output powers up to midscale. The device also has a

software power-down mode pin that reduces the typical current

consumption to less than 1 μA.

DAC ARCHITECTURE

The DAC architecture of the AD5063 consists of two matched

DAC sections. A simplified circuit diagram is shown in

Figure 27. The four MSBs of the 16-bit data-word are decoded

to drive 15 switches, E1 to E15. Each of these switches connects

one of 15 matched resistors to either the DACGND or VREF

buffer output. The remaining 12 bits of the data-word drive

Switches S0 to S11 of a 12-bit voltage mode R-2R ladder

network.

VREF

S11

E15

VOUT

12-BIT R-2R LADDER

FOUR MSBs DECODED INTO

15 EQUAL SEGMENTS

Figure 27. DAC Ladder Structure

REFERENCE BUFFER

The AD5063 operates with an external reference. The reference

input (VREF) has an input range of 2 V to AVDD − 50 mV. This

input voltage is used to provide a buffered reference for the

DAC core.

SERIAL INTERFACE

The AD5063 has a 3-wire serial interface (SYNC, SCLK, and

DIN) that is compatible with SPI, QSPI, and MICROWIRE

interface standards, as well as most DSPs. (See

for a

timing diagram of a typical write sequence.)

Figure 2

The write sequence begins by bringing the SYNC line low. Data

from the DIN line is clocked into the 24-bit shift register on the

falling edge of SCLK. The serial clock frequency can be as high

as 30 MHz, making these parts compatible with high speed

DSPs. On the 24th falling clock edge, the last data bit is clocked

in and the programmed function is executed (that is, a change

in the DAC register contents and/or a change in the mode of

operation).

At this stage, the SYNC line can be kept low or be brought

high. In either case, it must be brought high for a minimum of

12 ns before the next write sequence, so that a falling edge of

SYNC can initiate the next write sequence. Because the SYNC

buffer draws more current when VIH = 1.8 V than it does when

VIH = 0.8 V, SYNC should be idled low between write sequences

for even lower power operation of the part. As previously indi-

cated, however, it must be brought high again just before the

next write sequence.

INPUT SHIFT REGISTER

The input shift register is 24 bits wide (see Figure 28). PD1

and PD0 are bits that control the operating mode of the part

(normal mode or any one of the three power-down modes).

There is a more complete description of the various modes in

the Power-Down Modes section. The next 16 bits are the data

bits. These are transferred to the DAC register on the 24th falling

edge of SCLK.

SYNC INTERRUPT

In a normal write sequence, the SYNC line is kept low for at

least 24 falling edges of SCLK, and the DAC is updated on the

24th falling edge. However, if SYNC is brought high before the

24th falling edge, it acts as an interrupt to the write sequence.

The shift register is reset and the write sequence is seen as

invalid. Neither an update of the DAC register contents nor a

change in the operating mode occurs (see

Figure 31

DATA BITS

DB15 (MSB)

DB0 (LSB)

D15

D14

D13

D12

D11

D10

NORMAL OPERATION

1kΩ TO GND

100kΩ TO GND

THREE-STATE

POWER-DOWN MODES

PD1

PD0

Figure 28. Input Register Contents

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