EVAL-AD5063EB datasheet(14/20 Pages) AD

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AD5063

Rev. C | Page 14 of

POWER-ON TO MIDSCALE

The AD5063 contains a power-on reset circuit that controls the

output voltage during power-up. The DAC register is filled with

the midscale code, and the output voltage is midscale until a

valid write sequence is made to the DAC. This is useful in

applications where it is important to know the state of the DAC

output while it is in the process of powering up.

SOFTWARE RESET

The device can be put into software reset by setting all bits in

the DAC register to 1; this includes writing 1s to Bits D23 to

D16, which is not the normal mode of operation. Note that the

SYNC interrupt command cannot be performed if a software

reset command is started.

POWER-DOWN MODES

The AD5063 contains four separate modes of operation. These

modes are software-programmable by setting two bits (DB17

and DB16) in the control register. Table 6 shows how the state

of the bits corresponds to the operating mode of the device.

Table 6. Modes of Operation for the AD5063

DB17

DB16

Operating Mode

Normal operation

Power-down mode:

Three-state

100 kΩ to GND

1 kΩ to GND

When both bits are set to 0, the part has normal power con-

sumption. However, for the three power-down modes, the

supply current falls to 200 nA at 5 V (50 nA at 3 V). Not

only does the supply current fall, but the output stage is

also internally switched from the output of the amplifier to

a resistor network of known values. This has the advantage

that the output impedance of the part is known while the part

is in power-down mode. There are three options: The output

can be connected internally to GND through either a 1 kΩ

resistor or a 100 kΩ resistor, or it can be left open-circuited

(three-stated). The output stage is illustrated in Figure 29.

POWER-DOWN

CIRCUITRY

RESISTOR

NETWORK

VOUT

AD5063

DAC

Figure 29. Output Stage During Power-Down

The bias generator, DAC core, and other associated linear

circuitry are all shut down when the power-down mode is

activated. However, the contents of the DAC register are unaffected

when in power-down. The time to exit power-down is typically

2.5 μs for VDD = 5 V, and 5 μs for VDD = 3 V (see Figure 19).

MICROPROCESSOR INTERFACING

AD5063 to ADSP-2101/ADSP-2103 Interface

Figure 30 shows a serial interface between the AD5063 and the

ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should

be set up to operate in the SPORT transmit alternate framing

mode. The ADSP-2101/ADSP-2103 SPORT are programmed

through the SPORT control register and should be configured

as follows: internal clock operation, active low framing, and

16-bit word length. Transmission is initiated by writing a word

to the Tx register after the SPORT has been enabled.

AD5063

1ADDITIONAL PINS OMITTED FOR CLARITY

TFS

SCLK

SYNC

DIN

SCLK

ADSP-2101/

ADSP-21031

Figure 30. AD5063 to ADSP-2101/ADSP-2103 Interface

DB23

DB0

INVALID WRITE SEQUENCE:

SYNC HIGH BEFORE 24TH FALLING EDGE

VALID WRITE SEQUENCE:

OUTPUT UPDATES ON THE 24TH FALLING EDGE

SYNC

SCLK

DIN

Figure 31. SYNC Interrupt Facility

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