M68HC08 datasheet(106/332 Pages) FREESCALE

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System Integration Module (SIM)

Technical Data

MC68HC908JB16 — Rev. 1.1

106

System Integration Module (SIM)

Freescale Semiconductor

8.4.2.5 Low-Voltage Inhibit (LVI) Reset

The low-voltage inhibit module (LVI) asserts its output to the SIM when

the VDD or VREG voltage falls to the LVI reset voltage, VTRIP. The LVI bit

in the SIM reset status register (SRSR) is set, and the external reset pin

(RST) is held low while the SIM counter counts out 4096 OSCDCLK

cycles. Sixty-four OSCDCLK cycles later, the CPU is released from reset

to allow the reset vector sequence to occur. The SIM actively pulls down

the RST pin for all internal reset sources.

8.4.2.6 Universal Serial Bus (USB) Reset

The USB module will detect a reset signaled on the bus by the presence

of an extended SE0 at the USB data pins of a device. The MCU seeing

a single-ended 0 on its USB data inputs for more than 2.5

µs treats that

signal as a reset. After the reset is removed, the device will be in the

attached, but not yet addressed or configured, state (refer to Section 9.1

USB Devices of the Universal Serial Bus Specification Rev. 2.0). The

device must be able to accept the device address via a SET_ADDRESS

command (refer to Section 9.4 of the Universal Serial Bus Specification

Rev. 2.0) no later than 10ms after the reset is removed.

USB reset can be disabled to generate an internal reset. It can be

configured to generate IRQ interrupt. (See Section 5. Configuration

NOTE:

USB reset is disabled when the USB module is disabled by clearing the

USBEN bit of the USB address register (UADDR).

8.4.2.7 Registers Values After Different Resets

Some registers are reset by POR or LVI reset only. Table 8-3 shows the

registers or register bits which are unaffected by normal resets.

M68HC08 Datasheet(PDF) 106 Page - Freescale Semiconductor, Inc