M68HC08 datasheet(119/332 Pages) FREESCALE

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System Integration Module (SIM)

MC68HC908JB16 — Rev. 1.1

Technical Data

Freescale Semiconductor

System Integration Module (SIM)

119

8.8.2 SIM Reset Status Register (SRSR)

This register contains seven flags that show the source of the last reset.

All flag bits are cleared automatically following a read of the register. The

other bits cleared. However, during a POR or any other internal reset,

the RST pin is pulled low. After the pin is released, it will be sampled 32

OSCDCLK cycles later. If the pin is not above a VIH at that time, then the

PIN bit in the SRSR may be set in addition to whatever other bits are set.

POR — Power-On Reset Bit

1 = Last reset caused by POR circuit

0 = Read of SRSR

;

This code works if the H register has been pushed onto the stack in the break

service routine software. This code should be executed at the end of the break

service routine software.

HIBYTE

EQU

LOBYTE

EQU

;

If not SBSW, do RTI

BRCLR

SBSW,SBSR, RETURN

;

See if wait mode or stop mode was exited by

break.

TST

LOBYTE,SP

;If RETURNLO is not zero,

BNE

DOLO

;then just decrement low byte.

DEC

HIBYTE,SP

;Else deal with high byte, too.

DOLO

DEC

LOBYTE,SP

;Point to WAIT/STOP opcode.

RETURN

PULH

RTI

;Restore H register.

Address:

$FE01

Bit 7

654321

Bit 0

Read:

POR

COP

ILOP

ILAD

USB

LVI

Write:

POR:

10000000

= Unimplemented

Figure 8-20. SIM Reset Status Register (SRSR)

M68HC08 Datasheet(PDF) 119 Page - Freescale Semiconductor, Inc

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