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M68HC08 Datasheet(PDF) 115 Page - Freescale Semiconductor, Inc |
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M68HC08 Datasheet(HTML) 115 Page - Freescale Semiconductor, Inc |
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115 / 332 page ![]() System Integration Module (SIM) MC68HC908JB16 — Rev. 1.1 Technical Data Freescale Semiconductor System Integration Module (SIM) 115 Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This protection allows registers to be freely read and written during break mode without losing status flag information. Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains cleared even when break mode is exited. Status flags with a 2-step clearing mechanism — for example, a read of one register followed by the read or write of another — are protected, even when the first step is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step will clear the flag as normal. 8.7 Low-Power Modes Executing the WAIT or STOP instruction puts the MCU in a low-power- consumption mode for standby situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is described here. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur. 8.7.1 Wait Mode In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 8-14 shows the timing for wait mode entry. A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. Wait mode can also be exited by a reset or break. A break interrupt during wait mode sets the SIM break stop/wait bit, SBSW, in the SIM break status register (SBSR). If the COP disable bit, COPD, in the configuration register (CONFIG) is logic 0, then the computer operating properly module (COP) is enabled and remains active in wait mode. |
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