M68HC08 datasheet(116/332 Pages) FREESCALE

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System Integration Module (SIM)

Technical Data

MC68HC908JB16 — Rev. 1.1

116

System Integration Module (SIM)

Freescale Semiconductor

Figure 8-14. Wait Mode Entry Timing

Figure 8-15 and Figure 8-16 show the timing for WAIT recovery.

Figure 8-15. Wait Recovery from Interrupt or Break

Figure 8-16. Wait Recovery from Internal Reset

8.7.2 Stop Mode

In stop mode, the SIM counter is reset and the system clocks are

disabled. An interrupt request from a module can cause an exit from stop

mode. Stacking for interrupts begins after the selected stop recovery

time has elapsed. Reset or break also causes an exit from stop mode.

WAIT ADDR + 1

SAME

IAB

IDB

PREVIOUS DATA

NEXT OPCODE

SAME

WAIT ADDR

SAME

R/W

NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction

$6E0C

$6E0B

$00FF

$00FE

$00FD

$00FC

$A6

$01

$0B

$6E

$A6

IAB

IDB

EXITSTOPWAIT

NOTE: EXITSTOPWAIT = RST pin or CPU interrupt or break interrupt

IAB

IDB

RST

$A6

$6E0B

RST VCT H RST VCT L

$A6

OSCDCLK

CYCLES

M68HC08 Datasheet(PDF) 116 Page - Freescale Semiconductor, Inc

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