M68HC08 datasheet(112/332 Pages) FREESCALE

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System Integration Module (SIM)

Technical Data

MC68HC908JB16 — Rev. 1.1

112

System Integration Module (SIM)

Freescale Semiconductor

8.6.1.2 SWI Instruction

The SWI instruction is a non-maskable instruction that causes an

interrupt regardless of the state of the interrupt mask (I bit) in the

condition code register.

NOTE:

A software interrupt pushes PC onto the stack. A software interrupt does

not push PC–1, as a hardware interrupt does.

8.6.2 Interrupt Status Registers

The flags in the interrupt status registers identify maskable interrupt

sources. Table 8-4 summarizes the interrupt sources and the interrupt

status register flags that they set. The interrupt status registers can be

useful for debugging.

8.6.2.1 Interrupt Status Register 1

IF6–IF1 — Interrupt Flags 6–1

These flags indicate the presence of interrupt requests from the

sources shown in Table 8-4.

1 = Interrupt request present

0 = No interrupt request present

Bit 1 and Bit 0 — Always read 0

Address:

$FE04

Bit 7

654321

Bit 0

Read:

IF6

IF5

IF4

IF3

IF2

IF1

Write:

RRRRRRRR

Reset:

00000000

R= Reserved

Figure 8-12. Interrupt Status Register 1 (INT1)

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