EP3SE110 datasheet(168/341 Pages) ALTERA

168 / 341 page

1–158

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics

I/O Timing

Stratix III Device Handbook, Volume 2

Altera Corporation

1.2-V

HSTL

CLASS I

4mA

GCLK

tco

3.524

5.175

5.375

5.888

5.745

6.150 5.375 5.888 5.745 6.150

GCLK

PLL

3.923

5.810

6.015

6.592

6.420

6.907 6.015 6.592 6.420 6.907

6mA

GCLK

tco

3.516

5.166

5.366

5.879

5.736

6.141 5.366 5.879 5.736 6.141

GCLK

PLL

3.915

5.801

6.006

6.583

6.411

6.898 6.006 6.583 6.411 6.898

8mA

GCLK

3.517

5.174

5.374

5.888

5.745

6.150 5.374 5.888 5.745 6.150

GCLK

PLL

3.916

5.809

6.014

6.592

6.420

6.907 6.014 6.592 6.420 6.907

10mA

GCLK

3.506

5.161

5.361

5.874

5.731

6.136 5.361 5.874 5.731 6.136

GCLK

PLL

3.905

5.796

6.001

6.578

6.406

6.893 6.001 6.578 6.406 6.893

12mA

GCLK

3.506

5.161

5.361

5.875

5.732

6.137 5.361 5.875 5.732 6.137

GCLK

PLL

3.905

5.796

6.001

6.579

6.407

6.894 6.001 6.579 6.407 6.894

1.2-V

HSTL

CLASS II

16mA

GCLK

3.527

5.177

5.376

5.888

5.745

6.150 5.376 5.888 5.745 6.150

GCLK

PLL

tco

3.926

5.812

6.016

6.592

6.420

6.907 6.016 6.592 6.420 6.907

3.0-V PCI

—

GCLK

3.630

5.222

5.410

5.913

5.770

6.175 5.410 5.913 5.770 6.175

GCLK

PLL

tco

4.029

5.857

6.050

6.617

6.445

6.932 6.050 6.617 6.445 6.932

3.0-V

PCI-X

—

GCLK

3.630

5.222

5.410

5.913

5.770

6.175 5.410 5.913 5.770 6.175

GCLK

PLL

4.029

5.857

6.050

6.617

6.445

6.932 6.050 6.617 6.445 6.932

Table 1–83. EP3SL200 Column Pins Output Timing Parameters (Part 7 of 7)

I/O

Standard

Clock

Fast Model

C4L

I4L

Units

Industrial

Commercial

CCL=

1.1 V

CCL=

1.1 V

CCL=

1.1 V

CCL=

1.1 V

CCL=

0.9 V

CCL=

1.1 V

CCL=

1.1 V

CCL=

1.1 V

CCL=

0.9 V

EP3SE110 Datasheet(PDF) 168 Page - Altera Corporation

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