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EP3SE110 Datasheet(PDF) 172 Page - Altera Corporation |
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EP3SE110 Datasheet(HTML) 172 Page - Altera Corporation |
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172 / 341 page  1–162 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Stratix III Device Handbook, Volume 2 © July 2010 Altera Corporation 1.8-V HSTL CLASS I 4mA GCLK tco 3.458 3.720 5.479 5.692 6.268 6.108 6.453 5.839 6.402 6.108 6.453 ns GCLK PLL t co 1.381 1.568 2.008 2.093 2.296 2.305 2.241 2.212 2.415 2.305 2.241 ns 6mA GCLK t co 3.451 3.708 5.470 5.684 6.260 6.100 6.445 5.838 6.395 6.100 6.445 ns GCLK PLL tco 1.371 1.556 1.999 2.085 2.288 2.297 2.233 2.204 2.415 2.297 2.233 ns 8mA GCLK t co 3.442 3.696 5.462 5.675 6.252 6.092 6.438 5.831 6.387 6.092 6.438 ns GCLK PLL t co 1.362 1.544 1.991 2.076 2.280 2.289 2.225 2.196 2.408 2.289 2.225 ns 10mA GCLK t co 3.445 3.698 5.464 5.678 6.255 6.095 6.442 5.834 6.390 6.095 6.442 ns GCLK PLL t co 1.365 1.546 1.993 2.079 2.283 2.292 2.228 2.199 2.411 2.292 2.228 ns 12mA GCLK tco 3.441 3.693 5.462 5.677 6.255 6.095 6.445 5.837 6.395 6.095 6.445 ns GCLK PLL t co 1.361 1.541 1.991 2.081 2.283 2.292 2.228 2.202 2.416 2.292 2.228 ns 1.8-V HSTL CLASS II 16mA GCLK t co 3.449 3.697 5.457 5.669 6.246 6.086 6.441 5.833 6.389 6.086 6.441 ns GCLK PLL t co 1.369 1.545 1.986 2.078 2.274 2.283 2.219 2.198 2.410 2.283 2.219 ns 1.5-V HSTL CLASS I 4mA GCLK t co 3.464 3.727 5.490 5.705 6.283 6.123 6.468 5.848 6.416 6.123 6.468 ns GCLK PLL t co 1.388 1.575 2.019 2.106 2.311 2.320 2.256 2.224 2.426 2.320 2.256 ns 6mA GCLK t co 3.458 3.717 5.486 5.701 6.279 6.119 6.464 5.850 6.413 6.119 6.464 ns GCLK PLL t co 1.378 1.565 2.015 2.102 2.307 2.316 2.252 2.221 2.429 2.316 2.252 ns 8mA GCLK tco 3.454 3.712 5.480 5.695 6.273 6.113 6.458 5.845 6.407 6.113 6.458 ns GCLK PLL t co 1.374 1.560 2.009 2.096 2.301 2.310 2.246 2.215 2.423 2.310 2.246 ns 1.2-V HSTL CLASS I 4mA GCLK t co 3.466 3.726 5.501 5.719 6.301 6.141 6.486 5.864 6.433 6.141 6.486 ns GCLK PLL t co 1.387 1.574 2.030 2.120 2.329 2.338 2.274 2.238 2.445 2.338 2.274 ns 6mA GCLK t co 3.457 3.714 5.490 5.707 6.289 6.129 6.474 5.855 6.422 6.129 6.474 ns GCLK PLL t co 1.377 1.562 2.019 2.108 2.317 2.326 2.262 2.227 2.436 2.326 2.262 ns 8mA GCLK t co 3.456 3.712 5.494 5.712 6.295 6.135 6.480 5.864 6.429 6.135 6.480 ns GCLK PLL t co 1.376 1.560 2.023 2.113 2.323 2.332 2.268 2.233 2.446 2.332 2.268 ns 3.0-V PCI — GCLK tco 3.569 3.829 5.537 5.731 6.305 6.146 6.519 5.903 6.453 6.146 6.519 ns GCLK PLL t co 1.489 1.665 2.054 2.132 2.315 2.328 2.267 2.268 2.474 2.328 2.267 ns 3.0-V PCI-X — GCLK t co 3.569 3.829 5.537 5.731 6.305 6.146 6.519 5.903 6.453 6.146 6.519 ns GCLK PLL t co 1.489 1.665 2.054 2.132 2.315 2.328 2.267 2.268 2.474 2.328 2.267 ns Table 1–84. EP3SL200 Row Pins Output Timing Parameters (Part 4 of 4) I/O Standard Clock Fast Model C2 C3 C4 C4L I3 I4 I4L Units Industrial Commercial V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V |
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