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EP3SE110 Datasheet(PDF) 212 Page - Altera Corporation

Part # EP3SE110
Description  Stratix III Device Handbook
PDF  341 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP3SE110 Datasheet(HTML) 212 Page - Altera Corporation

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1–202
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Stratix III Device Handbook, Volume 2
© July 2010
Altera Corporation
Table 1–99 and Table 1–100 list the EP3SL340 regional (RCLK) clock adder values that
must be added to the GCLK values. Use these adder values to determine I/O timing
when the I/O pin is driven using the regional clock. This applies to all I/O standards
supported by Stratix III devices.
Table 1–99 lists the EP3SL340 column pin delay adders when using the regional clock.
Table 1–100 lists the EP3SL340 row pin delay adders when using the regional clock.
EP3SE50 I/O Timing Parameters
Table 1–101 through Table 1–104 list the maximum I/O timing parameters for
EP3SE50 devices for single-ended I/O standards.
Table 1–101 lists the EP3SE50 column pins input timing parameters for single-ended
I/O standards.
Table 1–99. EP3SL340 Column Pin Delay Adders for Regional Clock
Parameter
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
RCLK input adder
0.318
0.171
0.255
0.247
0.257
0.244
0.369
0.37
0.253
0.232
0.336
ns
RCLK PLL input adder
2.716
2.739
4.379
4.508
4.926
4.717
5.376
4.508
4.94
4.89
5.434
ns
RCLK output adder
-0.341
-0.107
-0.18
-0.169 -0.171 -0.167 -0.362
-0.03
-0.043 -0.034 -0.287
ns
RCLK PLL output adder
-2.36
-2.128
-3.344
-3.384 -3.571 -3.487 -3.545 -3.246 -3.636 -3.357 -3.544
ns
Table 1–100. EP3SL340 Row Pin Delay Adders for Regional Clock
Parameter
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
RCLK input adder
0.075
0.079
0.133
0.124
0.125
0.124
0.307
0.117
0.116
0.117
0.31
ns
RCLK PLL input adder
0.157
0.151
0.262
0.274
0.306
0.288
0.464
0.268
0.291
0.278
0.46
ns
RCLK output adder
-0.052
-0.066
-0.107 -0.098 -0.127 -0.129 -0.282 -0.082 -0.118 -0.085 -0.285
ns
RCLK PLL output adder
-0.157
-0.139
-0.232 -0.248 -0.272 -0.259 -0.422 -0.252 -0.256 -0.244 -0.444
ns
Table 1–101. EP3SE50 Column Pins Input Timing Parameters (Part 1 of 4)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
3.3-V LVTTL
GCLK
t
su
-0.743
-0.742
-1.063 -1.165 -1.374 -1.329 -1.605 -1.165
-1.374 -1.329
-1.605
ns
t
h
0.870
0.869
1.241
1.366
1.595
1.538
1.815
1.366
1.595
1.538
1.815
ns
GCLK
PLL
t
su
-1.037
-1.037
-1.466 -1.593 -1.830 -1.772 -2.038 -1.593
-1.830 -1.772
-2.038
ns
t
h
1.290
1.290
1.836
2.009
2.292
2.207
2.484
2.009
2.292
2.207
2.484
ns
3.3-V
LVCMOS
GCLK
t
su
-0.743
-0.742
-1.063 -1.165 -1.374 -1.329 -1.605 -1.165
-1.374 -1.329
-1.605
ns
t
h
0.870
0.869
1.241
1.366
1.595
1.538
1.815
1.366
1.595
1.538
1.815
ns
GCLK
PLL
t
su
-1.037
-1.037
-1.466 -1.593 -1.830 -1.772 -2.038 -1.593
-1.830 -1.772
-2.038
ns
t
h
1.290
1.290
1.836
2.009
2.292
2.207
2.484
2.009
2.292
2.207
2.484
ns



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