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EP3SE110 Datasheet(PDF) 214 Page - Altera Corporation

Part # EP3SE110
Description  Stratix III Device Handbook
PDF  341 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP3SE110 Datasheet(HTML) 214 Page - Altera Corporation

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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Stratix III Device Handbook, Volume 2
© July 2010
Altera Corporation
SSTL-18
CLASS II
GCLK
t
su
-0.672
-0.671
-0.971 -1.063 -1.166 -1.119 -1.398 -1.063
-1.166 -1.119
-1.398
ns
t
h
0.801
0.800
1.148
1.261
1.384
1.327
1.603
1.261
1.384
1.327
1.603
ns
GCLK
PLL
t
su
-0.968
-0.968
-1.373 -1.488 -1.619 -1.559 -1.828 -1.488
-1.619 -1.559
-1.828
ns
t
h
1.223
1.223
1.743
1.901
2.078
1.993
2.269
1.901
2.078
1.993
2.269
ns
SSTL-15
CLASS I
GCLK
t
su
-0.661
-0.660
-0.962 -1.052 -1.147 -1.100 -1.379 -1.052
-1.147 -1.100
-1.379
ns
t
h
0.790
0.789
1.138
1.250
1.365
1.308
1.584
1.250
1.365
1.308
1.584
ns
GCLK
PLL
t
su
-0.957
-0.957
-1.362 -1.477 -1.600 -1.540 -1.809 -1.477
-1.600 -1.540
-1.809
ns
t
h
1.212
1.212
1.731
1.890
2.059
1.974
2.250
1.890
2.059
1.974
2.250
ns
1.8-V HSTL
CLASS I
GCLK
t
su
-0.661
-0.660
-0.962 -1.052 -1.147 -1.100 -1.379 -1.052
-1.147 -1.100
-1.379
ns
t
h
0.790
0.789
1.138
1.250
1.365
1.308
1.584
1.250
1.365
1.308
1.584
ns
GCLK
PLL
t
su
-0.957
-0.957
-1.362 -1.477 -1.600 -1.540 -1.809 -1.477
-1.600 -1.540
-1.809
ns
t
h
1.212
1.212
1.731
1.890
2.059
1.974
2.250
1.890
2.059
1.974
2.250
ns
1.8-V HSTL
CLASS II
GCLK
t
su
-0.672
-0.671
-0.971 -1.063 -1.166 -1.119 -1.398 -1.063
-1.166 -1.119
-1.398
ns
t
h
0.801
0.800
1.148
1.261
1.384
1.327
1.603
1.261
1.384
1.327
1.603
ns
GCLK
PLL
t
su
-0.968
-0.968
-1.373 -1.488 -1.619 -1.559 -1.828 -1.488
-1.619 -1.559
-1.828
ns
t
h
1.223
1.223
1.743
1.901
2.078
1.993
2.269
1.901
2.078
1.993
2.269
ns
1.5-V HSTL
CLASS I
GCLK
t
su
-0.672
-0.671
-0.971 -1.063 -1.166 -1.119 -1.398 -1.063
-1.166 -1.119
-1.398
ns
t
h
0.801
0.800
1.148
1.261
1.384
1.327
1.603
1.261
1.384
1.327
1.603
ns
GCLK
PLL
t
su
-0.968
-0.968
-1.373 -1.488 -1.619 -1.559 -1.828 -1.488
-1.619 -1.559
-1.828
ns
t
h
1.223
1.223
1.743
1.901
2.078
1.993
2.269
1.901
2.078
1.993
2.269
ns
1.5-V HSTL
CLASS II
GCLK
t
su
-0.661
-0.660
-0.962 -1.052 -1.147 -1.100 -1.379 -1.052
-1.147 -1.100
-1.379
ns
t
h
0.790
0.789
1.138
1.250
1.365
1.308
1.584
1.250
1.365
1.308
1.584
ns
GCLK
PLL
t
su
-0.957
-0.957
-1.362 -1.477 -1.600 -1.540 -1.809 -1.477
-1.600 -1.540
-1.809
ns
t
h
1.212
1.212
1.731
1.890
2.059
1.974
2.250
1.890
2.059
1.974
2.250
ns
1.2-V HSTL
CLASS I
GCLK
t
su
-0.661
-0.660
-0.962 -1.052 -1.147 -1.100 -1.379 -1.052
-1.147 -1.100
-1.379
ns
t
h
0.790
0.789
1.138
1.250
1.365
1.308
1.584
1.250
1.365
1.308
1.584
ns
GCLK
PLL
t
su
-0.957
-0.957
-1.362 -1.477 -1.600 -1.540 -1.809 -1.477
-1.600 -1.540
-1.809
ns
t
h
1.212
1.212
1.731
1.890
2.059
1.974
2.250
1.890
2.059
1.974
2.250
ns
1.2-V HSTL
CLASS II
GCLK
t
su
-0.649
-0.648
-0.952 -1.041 -1.131 -1.084 -1.363 -1.041
-1.131 -1.084
-1.363
ns
t
h
0.778
0.777
1.128
1.239
1.349
1.292
1.568
1.239
1.349
1.292
1.568
ns
GCLK
PLL
t
su
-0.945
-0.945
-1.352 -1.466 -1.584 -1.524 -1.793 -1.466
-1.584 -1.524
-1.793
ns
t
h
1.200
1.200
1.721
1.879
2.043
1.958
2.234
1.879
2.043
1.958
2.234
ns
3.0-V PCI
GCLK
t
su
-0.649
-0.648
-0.952 -1.041 -1.131 -1.084 -1.363 -1.041
-1.131 -1.084
-1.363
ns
t
h
0.778
0.777
1.128
1.239
1.349
1.292
1.568
1.239
1.349
1.292
1.568
ns
GCLK
PLL
t
su
-0.945
-0.945
-1.352 -1.466 -1.584 -1.524 -1.793 -1.466
-1.584 -1.524
-1.793
ns
t
h
1.200
1.200
1.721
1.879
2.043
1.958
2.234
1.879
2.043
1.958
2.234
ns
Table 1–101. EP3SE50 Column Pins Input Timing Parameters (Part 3 of 4)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V



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