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EP3SE110 Datasheet(PDF) 231 Page - Altera Corporation |
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EP3SE110 Datasheet(HTML) 231 Page - Altera Corporation |
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231 / 341 page  Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics 1–221 I/O Timing © July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 Table 1–107 lists the EP3SE50 column pins output timing parameters for differential I/O standards. DIFFERENTIAL 2.5-V SSTL CLASS II GCLK tsu -0.762 -0.796 -1.128 -1.227 -1.336 -1.287 -1.561 -1.231 -1.336 -1.290 -1.593 ns t h 0.878 0.925 1.314 1.436 1.569 1.505 1.780 1.451 1.580 1.518 1.813 ns GCLK PLL t su 1.049 1.053 1.742 1.984 2.216 2.094 2.120 1.991 2.226 2.103 2.172 ns t h -0.796 -0.789 -1.341 -1.533 -1.709 -1.620 -1.638 -1.530 -1.710 -1.620 -1.688 ns Table 1–106. EP3SE50 Row Pins Input Timing Parameters (Part 3 of 3) I/O Standard Clock Fast Model C2 C3 C4 C4L I3 I4 I4L Units Industrial Commercial V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V Table 1–107. EP3SE50 Column Pins Output Timing Parameters (Part 1 of 4) I/O Standard Clock Fast Model C2 C3 C4 C4L I3 I4 I4L Units Industrial Commercial V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V LVDS_E_1R — GCLK tco 3.058 3.277 4.610 5.014 5.527 5.385 5.614 5.140 5.654 5.514 5.680 ns GCLK PLL t co 3.054 3.280 4.657 5.069 5.589 5.447 5.676 5.199 5.720 5.580 5.746 ns LVDS_E_3R — GCLK t co 3.058 3.277 4.610 5.014 5.527 5.385 5.614 5.140 5.654 5.514 5.680 ns GCLK PLL t co 3.054 3.280 4.657 5.069 5.589 5.447 5.676 5.199 5.720 5.580 5.746 ns MINI- LVDS_E_1R — GCLK t co 3.058 3.277 4.610 5.014 5.527 5.385 5.614 5.140 5.654 5.514 5.680 ns GCLK PLL t co 3.054 3.280 4.657 5.069 5.589 5.447 5.676 5.199 5.720 5.580 5.746 ns MINI- LVDS_E_3R — GCLK t co 3.085 3.310 4.681 5.092 5.611 5.469 5.698 5.220 5.740 5.600 5.766 ns GCLK PLL t co 3.075 3.300 4.671 5.081 5.601 5.459 5.688 5.209 5.730 5.590 5.756 ns RSDS_E_1R — GCLK tco 3.075 3.300 4.674 5.085 5.605 5.463 5.692 5.214 5.735 5.595 5.761 ns GCLK PLL t co 3.068 3.294 4.667 5.079 5.599 5.457 5.686 5.207 5.729 5.589 5.755 ns RSDS_E_3R — GCLK t co 3.067 3.292 4.664 5.076 5.596 5.454 5.683 5.204 5.725 5.585 5.751 ns GCLK PLL t co 3.089 3.314 4.685 5.096 5.615 5.473 5.702 5.224 5.745 5.605 5.771 ns |
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