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ELECTRICAL CHARACTERISTICS

TIMING REQUIREMENTS

TLV5636

SLAS223C – JUNE 1999 – REVISED APRIL 2004

over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted)

ANALOG OUTPUT DYNAMIC PERFORMANCE

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Fast

1

3

Output settling time (full scale)

µs

Slow

3.5

7

Fast

0.5

1.5

Output settling time, code to code

µs

Slow

1

2

Fast

8

SR

Slew rate

V/µs

Slow

1.5

DIN = 0 to 1,

Glitch energy

5

nV-s

SNR

Signal-to-noise ratio

71

75

S/(N+D)

Signal-to-noise + distortion

59

66

dB

THD

Total harmonic distortion

-67

-59

Spurious free dynamic range

59

69

(1)

Settling time is the time for the output signal to remain within +0.5 LSB of the final measured value for a digital input code change of

0x20 to 0xFDF and 0xFDF to 0x020 respectively. Assured by design; not tested.

(2)

Settling time is the time for the output signal to remain within +0.5 LSB of the final measured value for a digital input code change of one

count. Assured by design; not tested.

(3)

Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.

DIGITAL INPUTS

MIN

NOM

MAX

UNIT

Setup time, CS low before FS falling edge

10

ns

Setup time, FS low before first negative SCLK edge

8

ns

10

ns

rising edge of FS.

10

ns

time between FS rising edge and CS rising edge.

SCLK pulse duration high

25

ns

SCLK pulse duration low

25

ns

Setup time, data ready before SCLK falling edge

8

ns

Hold time, data held valid after SCLK falling edge

5

ns

FS duration high

25

ns

5