ADP2109

Data Sheet

Rev. B | Page 10 of 16

THEORY OF OPERATION

GND

FB

VIN

SW

EN

ADP2109

SOFT START

UNDERVOLTAGE

LOCKOUT

OSCILLATOR

THERMAL

SHUTDOWN

DRIVER

AND

ANTISHOOT-

THROUGH

PSM

COMP

LOW

CURRENT

PWM

COMP

GM ERROR

AMP

PWM/

PSM

CONTROL

Figure 26. Functional Block Diagram

The ADP2109 is a step-down dc-to-dc converter that uses a

fixed frequency and high speed current mode architecture. The

high switching frequency and tiny 5-ball WLCSP package allow

for a small step-down dc-to-dc converter solution.

The ADP2109 operates with an input voltage of 2.3 V to 5.5 V and

regulates an output voltage down to 1.0 V.

CONTROL SCHEME

The ADP2109 operates with a fixed frequency, current mode

PWM control architecture at medium to high loads for high

efficiency, but it shifts to a power save mode control scheme

at light loads, to lower the regulation power losses. When

operating in fixed frequency PWM mode, the duty cycle of the

integrated switches is adjusted and regulates the output voltage.

When operating in power save mode at light loads, the output

ripple. During part of this time, the converter is able to stop

switching and enters an idle mode, which improves conversion

efficiency.

PWM MODE

In PWM mode, the ADP2109 operates at a fixed frequency of

3 MHz, set by an internal oscillator. At the start of each oscillator

cycle, the PFET switch is turned on, putting a positive voltage

across the inductor. Current in the inductor increases until the

current sense signal crosses the peak inductor current threshold

that turns off the PFET switch and turns on the NFET syn-

chronous rectifier. This puts a negative voltage across the

inductor, causing the inductor current to decrease. The

synchronous rectifier stays on for the rest of the cycle. The

ADP2109 regulates the output voltage by adjusting the peak

inductor current threshold.

POWER SAVE MODE

The ADP2109 smoothly transitions to the power save mode

of operation when the load current decreases below the power

save mode current threshold. On entry to power save mode,

an offset is induced in the PWM regulation level, which makes

the output voltage rise. When it has reached a level of approx-

imately 1.5 % above the PWM regulation level, PWM operation

is turned off. At this point, both power switches are off and the

to the PWM regulation voltage, at which point the device drives

This process repeats while the load current is below the power

save mode current threshold.

Power Save Mode Current Threshold

The power save mode current threshold is set to 80 mA. The

ADP2109 employs a scheme that enables this current to remain

scheme also ensures that there is very little hysteresis between

the power save mode current threshold for entry to and exit

from the power save mode. The power save mode current

threshold has been optimized for excellent efficiency over

all load currents.