Data Sheet

AD5444/AD5446

Rev. E | Page 7 of 28

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

10

9

8

7

6

1

2

3

4

5

GND

SCLK

SDIN

SDO

AD5444/

AD5446

TOP VIEW

(Not to Scale)

SYNC

Figure 5. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

DAC Current Output.

2

DAC Analog Ground. This pin should normally be tied to the analog ground of the system.

3

GND

Ground Pin.

4

SCLK

Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock

input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked

into the shift register on the rising edge of SCLK.

5

SDIN

Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input.

By default on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow

the user to change the active edge to the rising edge.

6

SYNC

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC is taken low,

data is loaded to the shift register on the active edge of the following clocks. The output updates on the rising

edge of SYNC.

7

SDO

Serial Data Output. This pin allows a number of parts to be daisy-chained. By default, data is clocked into the shift

register on the falling edge and out via SDO on the rising edge of SCLK. Data is always clocked out on the

alternate edge to data loaded to the shift register.

8

Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.

9

DAC Reference Voltage Input.

10

DAC Feedback Resistor. Establishes voltage output for the DAC by connecting to an external amplifier output.