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Data Sheet

AD5444/AD5446

Rev. E | Page 15 of 28

GENERAL DESCRIPTION

DAC SECTION

The AD5444/AD5446 are 12-bit and 14-bit current output

DACs consisting of segmented (4 bits), inverting R– 2R ladder

configurations. A simplified diagram for the 12-bit AD5444

is shown in Figure 37.

S12

DAC DATA LATCHES

AND DRIVERS

RFB

IOUT1

IOUT2

VREF

Figure 37. Simplified Ladder

The feedback resistor (RFB) has a value of R. The value of R is

typically 9 kΩ (7 kΩ minimum, 11 kΩ maximum). If IOUT1 is

kept at the same potential as GND, a constant current flows in

each ladder leg, regardless of digital input code. Therefore, the

input resistance presented at VREF is always constant and nomi-

nally of value R. The DAC output (IOUT1) is code-dependent,

producing various resistances and capacitances. The external

amplifier choice should take into account the variation in

impedance generated by the DAC on the amplifiers inverting

input node.

Access is provided to the VREF, RFB, and both IOUT terminals of

the DAC, making the device extremely versatile and allowing it

to be configured in several different operating modes. For

example, the device provides unipolar output mode, 4-quadrant

multiplication in bipolar mode, and single-supply mode of

operation. Note that a matching switch is used in series with the

internal RFB. Power must be applied to VDD to achieve continuity

when measuring RFB.

CIRCUIT OPERATION

Unipolar Mode

Using a single op amp, the AD5444/AD5446 can easily be

configured to provide 2-quadrant multiplying operation or

a unipolar output voltage swing, as shown in Figure 38.

When an output amplifier is connected in unipolar mode, the

output voltage is given by

REF

OUT







where:

is the fractional representation of the digital word loaded to

the DAC:

= 0 to 4095 (12-bit AD5444)

= 0 to 16383 (14-bit AD5446)

is the number of bits.

Note that the output voltage polarity is opposite to the VREF

polarity for dc reference voltages.

This DAC is designed to operate with either negative or positive

reference voltages. The VDD power pin is used by the internal

digital logic only to drive the on and off states of the DAC

switches. The DAC is also designed to accommodate ac refer-

ence input signals in the range of −10 V to +10 V. With a fixed

+10 V reference, the circuit shown in Figure 38 provides a

unipolar 0 V to −10 V output voltage swing. When VIN is an

ac signal, the circuit performs 2-quadrant multiplication.

Table 5 shows the relationship between digital code and

expected output voltage for unipolar operation.

Table 5. Unipolar Code

Digital Input

Analog Output (V)

1111 1111 1111

−VREF (4095/4096)

1000 0000 0000

−VREF (2048/4096) = −VREF/2

0000 0000 0001

−VREF (1/4096)

0000 0000 0000

−VREF (0/4096) = 0

AD5444/

AD5446

NOTES

1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.

2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED,

IF A1 IS A HIGH SPEED AMPLIFIER.

IOUT1

IOUT2

VREF

VDD

VOUT = 0V TO –VREF

AGND

VDD

VREF

SDIN

SCLK

SYNC

MICROCONTROLLER

RFB

Figure 38. Unipolar Operation

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