AD8021 datasheet(22/28 Pages) AD

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AD5444/AD5446

Data Sheet

Rev. E | Page 22 of 28

80C51/80L51 to AD5444/AD5446 Interface

A serial interface between the DAC and the 80C51/80L51 is

shown in Figure 50. TxD of the 80C51/80L51 drives SCLK of

the DAC serial interface, while RxD drives the serial data line,

SDIN. P1.1 is a bit-programmable pin on the serial port and

is used to drive SYNC. When data is to be transmitted to the

switch, P1.1 is taken low. The 80C51/80L51 transmits data only

in 8-bit bytes; therefore, only eight falling clock edges occur in

the transmit cycle. To load data correctly to the DAC, P1.1 is

left low after the first eight bits are transmitted, and a second

write cycle is initiated to transmit the second byte of data.

Data on RxD is clocked out of the microcontroller on the rising

edge of TxD and is valid on the falling edge. As a result, no glue

logic is required between the DAC and microcontroller inter-

face. P1.1 is taken high following the completion of this cycle.

The 80C51/80L51 provides the LSB of its SBUF register as the

first bit in the data stream. The DAC input register requires its

data with the MSB as the first bit received. The transmit routine

should take this into account.

SCLK

TxD

8051*

SYNC

P1.1

SDIN

RxD

*ADDITIONAL PINS OMITTED FOR CLARITY

AD5444/AD5446*

Figure 50. 80C51/80L51 to AD5444/AD5446 Interface

MC68HC11 Interface to AD5444/AD5446 Interface

Figure 51 is an example of a serial interface between the DAC

and the MC68HC11 microcontroller. The serial peripheral

interface (SPI) on the MC68HC11 is configured for master

mode (MSTR) = 1, clock polarity bit (CPOL) = 0, and the clock

phase bit (CPHA) = 1. The SPI is configured by writing to the

SPI control register (SPCR); see the 68HC11 User Manual. SCK

of the 68HC11 drives the SCLK of the DAC interface, the MOSI

output drives the serial data line (SDIN) of the AD5444/AD5446.

The SYNC signal is derived from a port line (PC7). When data

is being transmitted to the AD5444/AD5446, the SYNC line is

taken low (PC7). Data appearing on the MOSI output is valid

on the falling edge of SCK. Serial data from the 68HC11 is

transmitted in 8-bit bytes with only eight falling clock edges

occurring in the transmit cycle. Data is transmitted MSB first.

To load data to the DAC, PC7 is left low after the first eight bits

are transferred, and a second serial write operation is performed

to the DAC. PC7 is taken high at the end of this procedure.

SCLK

SCK

AD5444/AD5446*

SYNC

PC7

SDIN

MOSI

MC68HC11*

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 51. MC68HC11 to AD5444/AD5446 Interface

If the user wants to verify the data previously written to the

input shift register, the SDO line can be connected to MISO of

the MC68HC11, and, with SYNC low, the shift register clocks

data out on the rising edges of SCLK.

MICROWIRE to AD5444/AD5446 Interface

Figure 52 shows an interface between the DAC and any

MICROWIRE-compatible device. Serial data is shifted out

on the falling edge of the serial clock, SK, and is clocked into

the DAC input shift register on the rising edge of SK, which

corresponds to the falling edge of the DAC SCLK.

SCLK

MICROWIRE*

SYNC

SDIN

*ADDITIONAL PINS OMITTED FOR CLARITY

AD5444/AD5446*

Figure 52. MICROWIRE to AD5444/AD5446 Interface

PIC16C6x/7x to AD5444/AD5446 Interface

The PIC16C6x/7x synchronous serial port (SSP) is configured

as an SPI master with the clock polarity bit (CKP) = 0. This is

done by writing to the synchronous serial port control register

(SSPCON); see the PIC16/17 Microcontroller User Manual.

In this example, I/O port RA1 is used to provide a SYNC

signal and enable the serial port of the DAC. This micro-

controller transfers only eight bits of data during each serial

transfer operation; therefore, two consecutive write operations

are required. Figure 53 shows the connection diagram.

SCLK

SCK/RC3

PIC16C6x/7x*

SYNC

RA1

SDIN

SDI/RC4

*ADDITIONAL PINS OMITTED FOR CLARITY

AD5444/AD5446*

Figure 53. PIC16C6x/7x to AD5444/AD5446 Interface

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