AD8021 datasheet(23/28 Pages) AD

23 / 28 page

Data Sheet

AD5444/AD5446

Rev. E | Page 23 of 28

PCB LAYOUT AND POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful considera-

tion of the power supply and ground return layout helps to

ensure the rated performance. The printed circuit boards on

which the AD5444/AD5446 are mounted should be designed

so the analog and digital sections are separated and confined to

certain areas of the board. If the DACs are in systems in which

multiple devices require a AGND-to-DGND connection, the

connection should be made at one point only. The star ground

point should be established as close as possible to the devices.

The DAC should have ample supply bypassing of 10 µF in

parallel with 0.1 µF on the supply located as close to the pack-

age as possible, ideally right up against the device. The 0.1 µF

capacitor should have low effective series resistance (ESR)

and effective series inductance (ESI), like the common ceramic

types that provide a low impedance path to ground at high

frequencies, to handle transient currents due to internal logic

switching. Low ESR, 1 µF to 10 µF tantalum or electrolytic

capacitors should also be applied at the supplies to minimize

transient disturbance and filter out low frequency ripple.

Fast switching signals such as clocks should be shielded with

digital ground to avoid radiating noise to other parts of the

board, and should never be run near the reference inputs.

Avoid crossover of digital and analog signals. Traces on oppo-

site sides of the board should run at right angles to each other.

This reduces the effects of feedthrough throughout the board.

A microstrip technique, by far the best, is not always possible

with a double-sided board. In this technique, the component

side of the board is dedicated to the ground plane, while signal

traces are placed on the solder side.

It is good practice to employ compact, minimum lead-length

PCB layout design. Leads to the input should be as short as

possible to minimize IR drops and stray inductance.

The PCB metal traces between VREF and RFB should also be

matched to minimize gain error. To maximize high frequency

performance, the I-to-V amplifier should be located as close

to the device as possible.

AD8021 Datasheet(PDF) 23 Page - Analog Devices