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ADV212 Datasheet(PDF) 12 Page - Analog Devices

Part # ADV212
Description  Wavescale Video Codec
PDF  44 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADV212 Datasheet(HTML) 12 Page - Analog Devices

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ADV212
Rev. B | Page 12 of 44
EXTERNAL DMA MODE—FIFO WRITE, BURST MODE
Table 8.
Parameter
Mnemonic
Min
Typ
Max
Unit
DREQ Pulse Width1
DREQPULSE
1 JCLK 2
15 JCLK2
ns
WE to DREQ Deassert (DR × PULS = 0)
t
DREQRTN
2.5 JCLK2
3.5 × JCLK + 7.52
ns
DACK to WE Setup
t
DACKSU
0
ns
Data Setup
tSU
2.5
ns
Data Hold
tHD
2
ns
WE Assert Pulse Width
WELOW
1.5 JCLK2
ns
WE Deassert Pulse Width
WEHIGH
1.5 JCLK2
ns
WE Deassert to Next DREQ
t
DREQWAIT
2.5 JCLK2
4.5 × JCLK + 9.02
ns
WE Deassert to DACK Deassert
t
WE_DACK
0
ns
1
Applies to assigned DMA channel, if EDMOD0/EDMOD1[14:11] is programmed to a nonzero value.
2
For a definition of JCLK, see Figure 32.
DREQ
DACK
WE
HDATA
WEHIGH
WELOW
tDACK
SU
tHD
tSU
0
1
13
14
15
tDREQ
WAIT
DREQPULSE
tWE_DACK
Figure 13. Burst Write Cycle for DREQ/DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1[14:1] Not Programmed to a Value of 0000)
DREQ
DACK
WE
WEHIGH
WELOW
tDACK
SU
tHD
tSU
0
1
13
14
15
tDREQ
WAIT
tDREQ
RTN
HDATA
tWE_DACK
Figure 14. Burst Write Cycle for DREQ/DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1[14:11] Programmed to a Value of 0000)
DREQ
DACK
WEFB
HDATA
WELOW
tDACK
SU
tHD
tSU
0
1
13
14
15
tDREQ
WAIT
WEHIGH
tWE_DACK
tDREQ
RTN
Figure 15. Burst Write Cycle for Fly-By DMA Mode



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