ADV212 datasheet(21/44 Pages) AD

21 / 44 page

ADV212

Rev. B | Page 21 of 44

121-Ball Package

144-Ball Package

Pin No.

Location

Pin No.

Location

Mnemonic

Pins

Used

Type

Description

G11

ACK

Acknowledge. Used for direct register accesses.

This signal indicates that the last register access

was successful. Due to synchronization issues,

control and status register accesses may incur an

additional delay; therefore, the host software

should wait for acknowledgment from the

ADV212 before attempting another register

access.

Accesses to the FIFOs (external DMA modes),

on the other hand, are guaranteed to occur

immediately, provided that space is available;

therefore, the host software does not need to

wait for ACK before attempting another register

access, provided that the timing constraints

are observed.

If ACK is shared with more than one device, ACK

should be connected to a pull-up resistor (10 k Ω)

and the PLL_HI register, Bit 4, must be set to 1.

G10

IRQ

Interrupt. This pin indicates that the ADV212

requires the attention of the host processor.

This pin can be programmed to indicate the

status of the internal interrupt conditions

within the ADV212. The interrupt sources are

enabled via the bits in the EIRQIE register.

F12

DREQ0

Data Request for External DMA Interface.

Indicates that the ADV212 is ready to

send/receive data to/from the FIFO assigned

to DMA Channel 0.

FSRQ0

FIFO Service Request. Used in DCS-DMA

mode. Service request from the FIFO assigned

to Channel 0 (asynchronous mode).

VALID

Valid Indication for JDATA Input/Output Stream.

Polarity of this pin is programmable in the

EDMOD0 register. VALID is always an output.

CFG1

Boot Mode Configuration. This pin is read on

reset to determine the boot configuration of

the on-board processor. The pin should be

tied to IOVDD through a 10 kΩ resistor.

F11

DACK0

Data Acknowledge for External DMA Interface.

Signal from the host CPU, which indicates that

the data transfer request (DREQ0) has been

acknowledged and that the data transfer can

proceed. This pin must be held high at all

times if the DMA interface is not used, even if

the DMA channels are disabled.

HOLD

External Hold Indication for JDATA Input/Output

Stream. Polarity is programmable in the

EDMOD0 register. This pin is always an input.

FCS0

FIFO Chip Select. Used in DCS-DMA mode.

Chip select for the FIFO assigned to Channel 0

(asynchronous mode).

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