Preliminary Specification

PE33241

Page 2 of 13

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Table 1. Pin Descriptions

Figure 2. Pin Configurations (Top View)

Figure 3. Package Type

48-lead 7x7 mm QFN

Pin No.

Pin Name

Interface Mode

Type

Description

1

Both

Note 1

Power supply input. Input may range from 2.65 to 2.95V. Bypassing recommended

2

R4

Direct

Input

R counter bit 4

3

R5

Direct

Input

R counter bit 5

4

A3

Direct

Input

A counter bit 3

5

N/C

Both

Note 3

No connect

6

GND

Both

Ground

7

M3

Direct

Input

M counter bit 3

8

M2

Direct

Input

M counter bit 2

9

M1

Direct

Input

M counter bit 1

10

M0

Direct

Input

M counter bit 0

11

Both

Note 1

Power supply input. Input may range from 2.65 to 2.95V. Bypassing recommended

12

GND

Both

Ground

13

M8

Direct

Input

M counter bit 8

14

M7

Direct

Input

M counter bit 7

15

SCLK

Serial

Input

Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “low”)

or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk

M6

Direct

Input

M counter bit 6

16

SDATA

Serial

Input

Binary serial data input. Input data entered MSB first

M5

Direct

Input

M counter bit 5

S_WR

Serial

Input

Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary

register data is transferred to the secondary register on S_WR or Hop_WR rising edge

M4

Direct

Input

M counter bit 4

17