PE33241 datasheet(6/13 Pages) PSEMI

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Preliminary Specification

PE33241

Page 6 of 13

Document No. DOC-15014-3 │ UltraCMOS® RFIC Solutions

Table 6. AC Characteristics: VDD = 2.65 to 2.95V, -40°C < TA < 85°C, unless otherwise specified (continued)

Symbol

Parameter

Condition

Min

Typical

Max

Unit

SSB phase noise 5/6 prescaler (Fin = 3 GHz, Fc = 50 MHz, LBW = 500 kHz)

N

Phase noise

100 Hz offset

-95

dBc/Hz

N

Phase noise

1 kHz offset

-102

dBc/Hz

N

Phase noise

10 kHz offset

-112

dBc/Hz

N

Phase noise

100 kHz offset

-116

dBc/Hz

SSB phase noise 10/11 prescaler (Fin = 3 GHz, Fc = 50 MHz, LBW = 500 kHz)

N

Phase noise

100 Hz offset

-92

dBc/Hz

N

Phase noise

1 kHz offset

-99

dBc/Hz

N

Phase noise

10 kHz offset

-109

dBc/Hz

N

Phase noise

100 kHz offset

-114

dBc/Hz

Phase noise figure of merit (FOM)

FOMflicker

Flicker figure of merit

5/6 prescaler

-263

dBc/Hz

10/11 prescaler

-260

dBc/Hz

FOMfloor

Floor figure of merit

5/6 prescaler

-230

dBc/Hz

10/11 prescaler

-228

dBc/Hz

FOMflicker

PNflicker = FOMflicker + 20log (fvco) - 10log (foffset)

dBc/Hz

FOMfloor

PNfloor = FOMfloor + 10log (fpfd) + 20log (fvco/fpfd)

dBc/Hz

FOMtotal

dBc/Hz

PNtotal = 10log (10 [PNflicker/10] + 10 [PNfloor/10])

Notes: 1. Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk specification

2. CMOS logic levels can be used to drive the reference input. If the VDD of the CMOS driver matches the VDD of the PLL IC, then the reference input can be DC

coupled. Otherwise, the reference input should be AC coupled. For sine-wave inputs, the minimum amplitude needs to be 0.5 Vpp. The maximum level should be

limited to prevent ESD diodes at the pin input from turning on. Diodes will turn on at one forward-bias diode drop above VDD or below GND. The DC voltage at the

Reference input is VDD/2

3. Parameter is guaranteed through characterization only and is not tested

4. Parameters below are not tested for die sales. These parameters are verified during the element evaluation

5. 0 dBm minimum is recommended for improved phase noise performance when sine-wave is applied

6. +2 dBm or higher is recommended for improved phase noise performance

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