AD7533

Rev. C | Page 8 of 12

OPERATION

UNIPOLAR BINARY CODE

Table 4. Unipolar Binary Operation

(2-Quadrant Multiplication)

Digital Input

Analog Output

MSB

LSB

1 1 1 1 1 1 1 1 1 1

⎟

⎠

⎞

⎜

⎝

⎛

−

1024

1023

REF

V

1 0 0 0 0 0 0 0 0 1

⎟

⎠

⎞

⎜

⎝

⎛

−

1024

513

REF

V

1 0 0 0 0 0 0 0 0 0

⎟

⎠

⎞

⎜

⎝

⎛

=

⎟

⎠

⎞

⎜

⎝

⎛

−

2

1024

512

REF

REF

V

V

0 1 1 1 1 1 1 1 1 1

⎟

⎠

⎞

⎜

⎝

⎛

−

1024

511

REF

V

0 0 0 0 0 0 0 0 0 1

⎟

⎠

⎞

⎜

⎝

⎛

−

1024

1

REF

V

0 0 0 0 0 0 0 0 0 0

0

1024

0

=

⎟

⎠

⎞

⎜

⎝

⎛

−

REF

V

Nominal LSB magnitude for the circuit of Figure 11 is given by

⎟

⎠

⎞

⎜

⎝

⎛

=

1024

1

REF

V

LSB

3

14

1

16

2

15

4

13

AD7533

UNIPOLAR

DIGITAL

INPUT

MSB

C1

GND

BIPOLAR

ANALOG INPUT

±10V

R1

1kΩ

R2

330Ω

LSB

NOTES

1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.

2. C1 PHASE COMPENSATION (5pF TO 15pF) MAY BE REQUIRED

WHEN USING HIGH SPEED AMPLIFIER.

Figure 11. Unipolar Binary Operation (2-Quadrant Multiplication)

BIPOLAR (OFFSET BINARY) CODE

Table 5. Unipolar Binary Operation

(4-Quadrant Multiplication)

Digital Input

Analog Output

MSB

LSB

1 1 1 1 1 1 1 1 1 1

⎟

⎠

⎞

⎜

⎝

⎛

+

512

511

REF

V

1 0 0 0 0 0 0 0 0 1

⎟

⎠

⎞

⎜

⎝

⎛

+

512

1

REF

V

1 0 0 0 0 0 0 0 0 0

0

0 1 1 1 1 1 1 1 1 1

⎟

⎠

⎞

⎜

⎝

⎛

−

512

1

REF

V

0 0 0 0 0 0 0 0 0 1

⎟

⎠

⎞

⎜

⎝

⎛

−

512

511

REF

V

0 0 0 0 0 0 0 0 0 0

⎟

⎠

⎞

⎜

⎝

⎛

−

512

512

REF

V

Nominal LSB magnitude for the circuit of Figure 12 is given by

⎟

⎠

⎞

⎜

⎝

⎛

=

512

1

REF

V

LSB

3

14

1

16

2

15

4

13

AD7533

BIPOLAR

DIGITAL

INPUT

MSB

C1

GND

A1

A2

±10V

BIPOLAR

ANALOG INPUT

R1

1kΩ

R2

330Ω

R3

10kΩ

R6

5kΩ

R4

20kΩ

LSB

NOTES

1. R3, R4, AND R5 SELECTED FOR MATCHING AND TRACKING.

2. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.

3. C1 PHASE COMPENSATION (5pF TO 15pF) MAY BE REQUIRED

WHEN USING HIGH SPEED AMPLIFIERS.

R5

20kΩ

Figure 12. Bipolar Operation (4-Quadrant Multiplication)