AD7477AARMZ datasheet(9/28 Pages) AD

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AD7476A/AD7477A/AD7478A

Rev. F | Page 9 of 28

Timing Diagrams

TO OUTPUT

50pF

200

µA

IOH

200

µA

IOL

1.6V

Figure 2. Load Circuit for Digital Output Timing Specifications

Timing Example 1

Having fSCLK = 20 MHz and a throughput of 1 MSPS, a cycle

time of

t2 + 12.5 (1/fSCLK) + tACQ = 1 µs

where:

t2 = 10 ns min, leaving tACQ to be 365 ns. This 365 ns satisfies the

requirement of 250 ns for tACQ.

From Figure 4, tACQ is comprised of

2.5 (1/fSCLK) + t8 + tQUIET

where:

t8 = 36 ns maximum. This allows a value of 204 ns for tQUIET,

satisfying the minimum requirement of 50 ns.

Timing Example 2

Having fSCLK = 5 MHz and a throughput is 315 kSPS yields a

cycle time of

t2 + 12.5 (1/fSCLK) + tACQ = 3.174 µs

where:

t2 = 10 ns min, this leaves tACQ to be 664 ns. This 664 ns satisfies

the requirement of 250 ns for tACQ.

From Figure 4, tACQ is comprised of

2.5 (1/fSCLK) + t8 + tQUIET, t8 = 36 ns maximum

This allows a value of 128 ns for tQUIET, satisfying the minimum

requirement of 50 ns.

In this example and with other, slower clock values, the signal

may already be acquired before the conversion is complete, but

it is still necessary to leave 50 ns minimum tQUIET between

conversions. In Example 2, acquire the signal fully at

approximately Point C in Figure 4.

SCLK

SDATA

tCONVERT

tQUIET

ZERO

DB11

DB10

DB2

DB1

DB0

THREE-STATE

THREE-

STATE

4 LEADING ZEROS

Figure 3. AD7476A Serial Interface Timing Diagram

SCLK

tCONVERT

tQUIET

tACQ

12.5(1/fSCLK)

1/THROUGHPUT

Figure 4. Serial Interface Timing Example

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