AD7477AARMZ datasheet(24/28 Pages) AD

24 / 28 page

AD7476A/AD7477A/AD7478A

Rev. F | Page 24 of 28

To implement the power-down mode, set SLEN to 0111 to issue

an 8-bit SCLK burst. The connection diagram is shown in

Figure 29. The ADSP-218x has the TFS and RFS of the SPORT

tied together, with TFS set as an output and RFS set as an input.

The DSP operates in alternate framing mode, and the SPORT

control register is set up as described. The frame synchronization

signal generated on the TFS is tied to CS, and, as with all signal

processing applications, equidistant sampling is necessary.

However, in this example, the timer interrupt is used to control

the sampling rate of the ADC and, under certain conditions,

equidistant sampling may not be achieved.

AD7476A/

AD7477A/

AD7478A1

SCLK

SDATA

SCLK

RFS

TFS

ADSP-218x1

1ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 29. Interfacing to the ADSP-218x

The timer registers, for example, are loaded with a value that

provides an interrupt at the required sample interval. When an

interrupt is received, a value is transmitted with TFS/DT (ADC

control word). The TFS controls the RFS and, thus, the reading

of data. The frequency of the serial clock is set in the SCLKDIV

that is, TX0 = AX0, the state of the SCLK is checked. The DSP

waits until the SCLK has gone high, low, and high before

transmission starts. If the timer and SCLK values are chosen

such that the instruction to transmit occurs on or near the

rising edge of SCLK, the data can be transmitted or it can wait

until the next clock edge. For example, the ADSP-2111 has a

master clock frequency of 16 MHz. If the SCLKDIV register is

loaded with the Value 3, an SCLK of 2 MHz is obtained and

eight master clock periods will elapse for every one SCLK

period. If the timer registers are loaded with the Value 803,

100.5 SCLKs occur between interrupts and, subsequently,

between transmit instructions. This situation results in

nonequidistant sampling as the transmit instruction is

occurring on an SCLK edge. If the number of SCLKs between

interrupts is a whole integer figure of N, equidistant sampling is

implemented by the DSP.

AD7476A/AD7477A/AD7478A TO DSP563xx

INTERFACE

The connection diagram in Figure 30 shows how the

AD7476A/AD7477A/AD7478A can be connected to the SSI

(synchronous serial interface) of the DSP563xx family of DSPs

from Motorola. The SSI is operated in synchronous and normal

mode (SYN 1 = and MOD = 0 in Control Register B, CRB) with

internally generated word length frame sync for both Tx and Rx

(Bit FSL1 = 0 and Bit FSL0 = 0 in CRB). Set the word length in

Control Register A (CRA) to 16 by setting Bit WL2 = 0, Bit

WL1 = 1, and Bit WL0 = 0 for the AD7476A. The word length

for the AD7478A can be set to 12 bits (WL2 = 0, WL1 = 0, and

WL0 = 1). This DSP does not offer the option for a 14-bit word

length, so the AD7477A word length is set up to 16 bits, the

same as the AD7476A. For the AD7477A, the conversion process

uses 16 SCLK cycles, with the last two clock periods clocking out

two trailing zeros to fill the 16-bit word.

To implement the power-down mode on the AD7476A/AD7477A/

AD7478A, the word length can be changed to eight bits by setting

Bit WL2 = 0, Bit WL1 = 0, and Bit WL0 = 0 in CRA. The FSP

bit in the CRB register can be set to 1, meaning the frame goes

low and a conversion starts. Likewise, by means of the Bit SCD2,

Bit SCKD, and Bit SHFD in the CRB register, it establishes that

Pin SC2 (the frame sync signal) and Pin SCK in the serial port

are configured as outputs and the MSB is shifted first.

In summary:

MOD = 0

SYN = 1

WL2, WL1, and WL0 depend on the word length

FSL1 = 0 and FSL0 = 0

FSP = 1, negative frame sync

SCD2 = 1

SCKD = 1

SHFD = 0

Note that for signal processing applications, it is imperative that

the frame synchronization signal from the DSP563xx provide

equidistant sampling.

AD7476A/

AD7477A

AD7478A1

SDATA

SCLK

DSP563xx1

SCK

SRD

SC2

1ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 30. Interfacing to the DSP563xx

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