PCA9535EC datasheet(6/20 Pages) ONSEMI

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PCA9535E, PCA9535EC

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Table 5. AC ELECTRICAL CHARACTERISTICS VDD = 1.65 V to 5.5 V; TA = −55°C to +125°C, unless otherwise specified.

Symbol

Parameter

Standard Mode

Fast Mode

Fast Mode +

Unit

Min

Max

Min

Max

Min

Max

fSCL

SCL Clock Frequency

0.1

0.4

1.0

MHz

tBUF

Bus−Free Time between a STOP and START

Condition

4.7

1.3

0.5

tHD:STA

Hold Time (Repeated) START Condition

4.0

0.6

0.26

tSU:STA

Setup Time for a Repeated START Condition

4.7

0.6

0.26

tSU:STO

Setup Time for STOP Condition

4.0

0.6

0.26

tHD:DAT

Data Hold Time

tVD:ACK

Data Valid Acknowledge Time (Note 10)

0.3

3.45

0.1

0.9

0.05

0.45

tVD:DAT

Data Valid Time (Note 11)

300

450

tSU:DAT

Data Setup Time

250

100

tLOW

LOW Period of SCL

4.7

1.3

0.5

tHIGH

HIGH Period of SCL

4.0

0.6

0.26

Fall Time of SDA and SCL (Notes 13 and 14)

300

20 +

0.1Cb

(Note 12)

300

120

Rise Time of SDA and SCL

1000

20 +

0.1Cb

(Note 12)

300

120

tSP

Pulse Width of Spikes Suppressed by Input

Filter (Note 15)

PORT TIMING: CL v 100 pF (See Figures 6, 9 and 10)

tV(Q)

Data Output Valid Time (VDD = 4.5 V to 5.5 V)

(VDD = 2.3 V to 4.5 V)

(VDD = 1.65 V to 2.3 V)

200

350

550

200

350

550

200

350

550

tSU(D)

Data Input Setup Time

100

tH(D)

Data Input Hold Time

INTERRUPT TIMING: CL v 100 pF (See Figures 9 and 10)

tV(INT_N)

Data Valid Time

tRST(INT_N)

Reset Delay Time

10.tVD:ACK = time for Acknowledgment signal from SCL LOW to SDA (out) LOW.

11. tVD:DAT = minimum time for SDA data out to be valid following SCL LOW.

12.Cb = total capacitance of one bus line in pF.

13.A master device must internally provide a hold time of al least 300 ns for the SDA signal (refer to VIL of the SCL signal) in order to bridge

the undefined region SCL’s falling edge.

14.The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at

250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without

exceeding the maximum specified tf.

15.Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.

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