PCA9535EC datasheet(10/20 Pages) ONSEMI

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PCA9535E, PCA9535EC

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Registers 4 and 5: Polarity Inversion Registers

These registers allow the polarity of the data in the input

port registers to be inverted. The input port data polarity will

be inverted when its corresponding bit in these registers is

set (written with ‘1’), and retained when the bit is cleared

(written with a ‘0’).

Table 12. POLARITY INVERSION PORT 0 REGISTER

Bit

Symbol

N0.7

N0.6

N0.5

N0.4

N0.3

N0.2

N0.1

N0.0

Default

Table 13. POLARITY INVERSION PORT 1 REGISTER

Bit

Symbol

N1.7

N1.6

N1.5

N1.4

N1.3

N1.2

N1.1

N1.0

Default

Registers 6 and 7: Configuration Registers

The I/O pin directions are configured through the

configuration registers. When a bit in the configuration

registers is set (written with ‘1’), the bit’s corresponding port

pin is enabled as an input with the output driver in

high−impedance. When a bit is cleared (written with ‘0’),

the corresponding port pin is enabled as an output. At reset,

the device’s ports are inputs.

Table 14. CONFIGURATION PORT 0 REGISTER

Bit

Symbol

C0.7

C0.6

C0.5

C0.4

C0.3

C0.2

C0.1

C0.0

Default

Table 15. CONFIGURATION PORT 1 REGISTER

Bit

Symbol

C1.7

C1.6

C1.5

C1.4

C1.3

C1.2

C1.1

C1.0

Default

Power−on Reset

Upon application of power, an internal Power−On Reset

(POR) holds the PCA9535E/PCA9535EC in a reset

condition while VDD is ramping up. When VDDhas reached

VPOR, the reset condition is released and the

PCA9535E/PCA9535EC registers and SMBus state

machine will initialize to their default states. The reset is

typically completed by the POR and the part enabled by the

time the power supply is above VPOR. However, when doing

a power reset cycle, it is necessary to lower the power supply

below 0.2 V, and then restored to the operating voltage.

I/O Port (See Figure 2)

When an I/O pin is configured as an input on the

PCA9535E, FETs Q1 and Q2 are off, creating a

high−impedance input. The input voltage may be raised

above VDD to a maximum of 5.5 V. In the case of

PCA9535EC, FET Q1 has been removed and the

open−drain FET Q2 will function the same as PCA9535E.

When the I/O pin is configured as an output on the

PCA9535E, then either Q1 or Q2 is enabled, depending on

the state of the output port register. With the PCA9535EC,

an external pullup is required to pull the I/O pin HIGH when

its corresponding output port register bit is a 1. Care should

be exercised if an external voltage is applied to an I/O

configured as an output because of the low−impedance path

that exists between the pin and either VDD or VSS.

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