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DIGITAL INTERFACE

Timing And Control

Reading Data

ADS8406

SLAS426A – AUGUST 2004 – REVISED DECEMBER 2004

PRINCIPLES OF OPERATION (continued)

See the timing diagrams in the specifications section for detailed information on timing signals and their

requirements.

The ADS8406 uses an internal oscillator generated clock which controls the conversion rate and in turn the

throughput of the converter. No external clock input is required.

Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimum

requirement has been met, the CONVST pin can be brought high), while CS is low. The ADS8406 switches from

the sample to the hold mode on the falling edge of the CONVST command. A clean and low jitter falling edge of

this signal is important to the performance of the converter. The BUSY output is brought high after CONVST

goes low. BUSY stays high throughout the conversion process and returns low when the conversion has ended.

Sampling starts as soon as the conversion is over when CS is tied low or starts with the falling edge of CS when

BUSY is low.

Both RD and CS can be high during and before a conversion with one exception (CS must be low when

CONVST goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the

parallel output bus with the conversion.

The ADS8406 outputs full parallel data in two's complement format as shown in Table 1. The parallel output is

active when CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of

CONVST. This is 50 ns prior to the falling edge of CONVST and 40 ns after the falling edge. No data read should

be attempted within this zone. Any other combination of CS and RD sets the parallel output to 3-state. BYTE is

used for multiword read operations. BYTE is used whenever lower bits of the converter result are output on the

higher byte of the bus. Refer to Table 1 for ideal output codes.

Table 1. Ideal Input Voltages and Output Codes

DESCRIPTION

ANALOG VALUE

DIGITAL OUTPUT

Full scale range

2'S COMPLEMENT

Least significant bit (LSB)

BINARY CODE

HEX CODE

+Full scale

0111 1111 1111 1111

7FFF

Midscale

0 V

0000 0000 0000 0000

0000

Midscale – 1 LSB

0 V– 1 LSB

1111 1111 1111 1111

FFFF

– Full scale

1000 0000 0000 0000

8000

The output data is a full 16-bit word (D15–D0) on DB15–DB0 pins (MSB–LSB) if BYTE is low.

The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB15–DB8. In this

case two reads are necessary: the first as before, leaving BYTE low and reading the 8 most significant bits on

pins DB15–DB8, then bringing BYTE high. When BYTE is high, the low bits (D7–D0) appear on pins DB15–D8.

These multiword read operations can be done with multiple active RD (toggling) or with RD tied low for simplicity.

Conversion Data Readout

DATA READ OUT

BYTE

DB15–DB8 Pins

DB7–DB0 Pins

High

D7–D0

All one's

Low

D15–D8

D7–D0

20