DDC112

11

SBAS085B

www.ti.com

The value of the integrator’s feedback capacitor, the integra-

tion period, and the reference voltage determine the positive

full-scale (+FS) value of the DDC112. The approximate

positive full-scale value of the DDC112 is given by the

following equations:

QI

T

QV

C

I

VC

T

or

C

IT

V

IN

IN

INT

FS

REF

F

FS

REF

F

INT

F

FS

INT

REF

=×

=

(

)

×

)

×

=

×

096

096

096

.

.

(.

)

The

0.96 factor allows the front end integrators to reach full-

scale without having to completely swing to ground. The

negative full-scale (–FS) range is approximately 0.4% of the

positive full-scale range. For example, Range 5 has a nomi-

nal +FS range of 250pC. The –FS range is then approxi-

mately –1pC. This relationship holds for external capacitors

allowable range, see the Electrical Characteristics table).

Integration Capacitors

There are seven different capacitors available on-chip for

each side of each channel in the DDC112. These internal

capacitors are trimmed in production to achieve the specified

performance for range error of the DDC112. The range

control pins (RANGE0-RANGE2) change the capacitor value

for all four integrators. Consequently, both inputs and both

sides of each input will always have the same full-scale

range unless external capacitors are used.

External integration capacitors may be used instead of the

internal capacitors values by setting [RANGE2-RANGE0 =

000]. The external capacitor pin connections are summa-

rized in Table II. Usually, all four external capacitors are

equal in value; however, it is possible to have differing pairs

of external capacitors between Input 1 and Input 2 of the

DDC112. Regardless of the selected value of the capacitor,

it is strongly recommended that the capacitors for sides A

and B be the same.

INTEGRATOR

DDC112U, UK

DDC112Y, YK

Channel

Side

5 and 6

1 and 2

1

A

3 and 4

31 and 32

1

B

23 and 24

23 and 24

2

A

25 and 26

25 and 26

2

B

TABLE II. External Capacitor Connections with Range Con-

figuration of RANGE2-RANGE0 = 000.

Since the range accuracy depends on the characteristics of

the integration capacitor, they must be carefully selected. An

external integration capacitor should have low-voltage coef-

ficient, temperature coefficient, memory, and leakage cur-

rent. The optimum selection depends on the requirements of

the specific application. Suitable types include chip-on-glass

(COG) ceramic, polycarbonate, polystyrene, and silver mica.

Voltage Reference

The external voltage reference is used to reset the integra-

tion capacitors before an integration cycle begins. It is also

used by the

∆Σ converter while the converter is measuring

the voltage stored on the integrators after an integration

cycle ends. During this sampling, the external reference must

supply charge needed by the

∆Σ converter. For an integration

time of 500

µs, this charge translates to an average V

REF

current of approximately 150

µA. The amount of charge

needed by the

∆Σ converter is independent of the integration

time; therefore, increasing the integration time lowers the

average current. For example, an integration time of 1000

µs

operation in Figure 5. The

∆Σ converter measures the volt-

the converter measures the integrator’s output will introduce

duce as little additional noise as possible.

For reasons mentioned above, it is strongly recommended

that the external reference source be buffered with an

operational amplifier, as shown in Figure 6. In this circuit,

the voltage reference is generated by a 4.096V reference.

FIGURE 6. Recommended External Voltage Reference Circuit for Best Low-Noise Operation with the DDC112.

0.10

µF

+5V

10k

Ω

10

µF

4

3

3

2

1

2

7

6

+

0.10

µF

0.1

µF

10

µF

+

OPA350

To V

REF

Pin 22 of

the DDC112

REF3040

+5V

0.47

µF

EXTERNAL CAPACITOR PINS