AD9822JRZ datasheet(4/20 Pages) AD

4 / 20 page

AD9822

Rev. B | Page 4 of 20

Parameter

Min

Typ

Max

Unit

POWER DISSIPATION

3-Channel Mode

385

450

3-Channel Mode @ 6 MHz

335

410

1-Channel Mode

300

1-Channel Mode @ 6 MHz

250

1 Linear input signal range is from 2 V to 4 V when the CCD’s reference level is clamped to 4 V by the AD9822’s input clamp.

1V TYP

RESET TRANSIENT

4V SET BY INPUT CLAMP (3V OPTION ALSO AVAILABLE)

2V p-p MAX INPUT SIGNAL RANGE

2 The PGA gain is approximately linear-in-dB and follows the equation:

[

]

⎥

⎦

⎤

⎢

⎣

⎡

−

Gain

where G is the register value. See Figure

DIGITAL SPECIFICATIONS

TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V, CDS mode, fADCCLK = 15 MHz, fCDSCLK1 = fCDSCLK2 = 5 MHz, CL = 10 pF, unless otherwise noted.

Table 2.

Parameter

Symbol

Min

Typ

Max

Unit

LOGIC INPUTS

High Level Input Voltage

VIH

2.0

Low Level Input Voltage

VIL

0.8

High Level Input Current

IIH

µA

Low Level Input Current

IIL

µA

Input Capacitance

CIN

LOGIC OUTPUTS

High Level Output Voltage

VOH

4.5

Low Level Output Voltage

VOL

0.1

High Level Output Current

IOH

µA

Low Level Output Current

IOL

µA

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