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AD9822JRZ Datasheet(PDF) 5 Page - Analog Devices

Part # AD9822JRZ
Description  Complete 14-Bit CCD/CIS Signal Processor
PDF  20 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9822JRZ Datasheet(HTML) 5 Page - Analog Devices

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AD9822
Rev. B | Page 5 of 20
TIMING SPECIFICATIONS
TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V.
Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
CLOCK PARAMETERS
3-Channel Pixel Rate
tPRA
67
ns
1-Channel Pixel Rate
tPRB
80
ns
ADCCLK Pulse Width
tADCLK
30
ns
CDSCLK1 Pulse Width
tC1
10
ns
CDSCLK2 Pulse Width
tC2
10
ns
CDSCLK1 Falling to CDSCLK2 Rising
tC1C2
0
ns
ADCCLK Falling to CDSCLK2 Rising
tADC2
0
ns
CDSCLK2 Rising to ADCCLK Rising
tC2ADR
0
ns
CDSCLK2 Falling to ADCCLK Falling
tC2ADF
30
40
ns
CDSCLK2 Falling to CDSCLK1 Rising
tC2C1
30
40
ns
ADCCLK Falling to CDSCLK1 Rising
tADC1
0
ns
Aperture Delay for CDS Clocks
tAD
2
ns
SERIAL INTERFACE
Maximum SCLK Frequency
fSCLK
10
MHz
SLOAD to SCLK Setup Time
tLS
10
ns
SCLK to SLOAD Hold Time
tLH
10
ns
SDATA to SCLK Rising Setup Time
tDS
10
ns
SCLK Rising to SDATA Hold Time
tDH
10
ns
SCLK Falling to SDATA Valid
tRDV
10
ns
DATA OUTPUT
Output Delay
tOD
8
ns
Three-State to Data Valid
tDV
10
ns
Output Enable High to Three-State
tHZ
10
ns
Latency (Pipeline Delay)
3 (Fixed)
Cycles



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