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AD9773-EB Datasheet(PDF) 5 Page - Analog Devices

Part # AD9773-EB
Description  12-Bit, 160 MSPS, 2x/4x/8x Interpolating Dual TxDAC D/A Converter
PDF  60 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9773-EB Datasheet(HTML) 5 Page - Analog Devices

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AD9773
Rev. D | Page 5 of 60
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
RESOLUTION
12
Bits
DC Accuracy1
Integral Nonlinearity
−1.5
±0.4
+1.5
LSB
Differential Nonlinearity
−1
±0.2
+1
LSB
Monotonicity
Guaranteed over specified temperature range
ANALOG OUTPUT (for IR and 2R Gain Setting Modes)
Offset Error
−0.02
±0.01
+0.02
% of FSR
Gain Error (with Internal Reference)
−1.0
+1.0
% of FSR
Gain Matching
−1.0
±0.1
+1.0
% of FSR
Full-Scale Output Current2
2
20
mA
Output Compliance Range
−1.0
+1.25
V
Output Resistance
200
kΩ
Output Capacitance
3
pF
Gain, Offset Cal DACs, Monotonicity Guaranteed
REFERENCE OUTPUT
Reference Voltage
1.14
1.20
1.26
V
Reference Output Current3
100
nA
REFERENCE INPUT
Input Compliance Range
0.1
1.25
V
Reference Input Resistance
7
kΩ
Small Signal Bandwidth
0.5
MHz
TEMPERATURE COEFFICIENTS
Offset Drift
0
ppm of FSR/°C
Gain Drift (With Internal Reference)
50
ppm of FSR/°C
Reference Voltage Drift
±50
ppm/°C
POWER SUPPLY
AVDD
Voltage Range
3.1
3.3
3.5
V
Analog Supply Current (IAVDD)4
72.5
76
mA
IAVDD in Sleep Mode
23.3
26
mA
CLKVDD
Voltage Range
3.1
3.3
3.5
V
Clock Supply Current (ICLKVDD)4
8.5
10.0
mA
CLKVDD (PLL ON)
Clock Supply Current (ICLKVDD)
23.5
mA
DVDD
Voltage Range
3.1
3.3
3.5
V
Digital Supply Current (IDVDD)4
34
41
mA
Nominal Power Dissipation
380
410
mW
PDIS5
1.75
W
PDIS in PWDN
6.0
mW
Power Supply Rejection Ratio—AVDD
±0.4
% of FSR/V
OPERATING RANGE
−40
+85
°C
1 Measured at IOUTA driving a virtual ground.
2 Nominal full-scale current, IOUTFS, is 32× the IREF current.
3 Use an external amplifier to drive any external load.
4 100 MSPS fDAC with fOUT = 1 MHz, all supplies = 3.3 V, no interpolation, no modulation.
5 400 MSPS fDAC, fDATA = 50 MSPS, fS/2 modulation, PLL enabled.



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