AD9773-EB datasheet(28/60 Pages) AD

28 / 60 page

AD9773

Rev. D | Page 28 of 60

AD9773

PLLVDD

INPUT

DATA

LATCHES

PLL_LOCK

1 = LOCK

0 = NO LOCK

SPI PORT

LPF

CLK+

CLK–

INTERPOLATION

FILTERS,

MODULATORS,

AND DACS

CLOCK

DISTRIBUTION

CIRCUITRY

INTERPOLATION

RATE

CONTROL

INTERNAL SPI

CONTROL

REGISTERS

MODULATION

RATE

CONTROL

PLL

CONTROL

(PLL ON)

PLL DIVIDER

(PRESCALER)

CONTROL

PRESCALER

VCO

PHASE

DETECTOR

CHARGE

PUMP

Figure 45. PLL and Clock Circuitry with PLL Enabled

AD9773

INPUT

DATA

LATCHES

PLL_LOCK

1 = LOCK

0 = NO LOCK

SPI PORT

CLK+

CLK–

INTERPOLATION

FILTERS,

MODULATORS,

AND DACS

CLOCK

DISTRIBUTION

CIRCUITRY

INTERPOLATION

RATE

CONTROL

INTERNAL SPI

CONTROL

REGISTERS

MODULATION

RATE

CONTROL

PLL

CONTROL

(PLL ON)

PLL DIVIDER

(PRESCALER)

CONTROL

PRESCALER

VCO

PHASE

DETECTOR

CHARGE

PUMP

Figure 46. PLL and Clock Circuitry with PLL Disabled

In addition, if the zero stuffing option is enabled, the VCO

doubles its speed again. Phase noise may be slightly higher with

the PLL enabled. Figure 47 illustrates typical phase noise

performance of the AD9773 with 2× interpolation and various

input data rates. The signal synthesized for the phase noise

measurement was a single carrier at a frequency of fDATA/4. The

repetitive nature of this signal eliminates quantization noise and

distortion spurs as a factor in the measurement. Although the

curves blend together in Figure 47, the different conditions are

given for clarity in Table 17. Table 16 details PLL divider

settings vs. interpolation rate and maximum and minimum

fDATA rates. Note that the maximum fDATA rates of 160 MSPS are

due to the maximum input data rate of the AD9773.

However, maximum rates of less than 160 MSPS and all

minimum fDATA rates are due to the maximum and minimum

speeds of the internal PLL VCO. Figure 48 shows typical

performance of the PLL lock signal (Pin 8 or Pin 53) when the

PLL is in the process of locking.

Table 16. PLL Optimization

Interpolation

Rate

Divider

Setting

Minimum

fDATA

Maximum

fDATA

160

112

160

112

100

Table 17. Required PLL Prescaler Ratio vs. fDATA

fDATA

PLL

Prescaler Ratio

125 MSPS

Disabled

125 MSPS

Enabled

Div 1

100 MSPS

Enabled

Div 2

75 MSPS

Enabled

Div 2

50 MSPS

Enabled

Div 4

–110

–100

–80

–40

–20

–60

–90

–50

–30

–10

–70

012

FREQUENCY OFFSET (MHz)

Figure 47. Phase Noise Performance

AD9773-EB Datasheet(PDF) 28 Page - Analog Devices

AD9773-EB Datasheet(HTML) 28 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Download

Link URL