AD9773-EB datasheet(25/60 Pages) AD

25 / 60 page

AD9773

Rev. D | Page 25 of 60

NOTES ON SERIAL PORT OPERATION

The AD9773 serial port configuration bits reside in Bits 6 and 7

of Register Address 00h. It is important to note that the config-

uration changes immediately upon writing to the last bit of the

occur during the middle of the communication cycle. Care

must be taken to compensate for this new configuration for the

remaining bytes of the current communication cycle.

The same considerations apply to setting the reset bit in

values, but the software reset does not affect the bits in

It is recommended to use only single-byte transfers when changing

serial port configurations or initiating a software reset.

A write to Bit 1, Bit 2, and Bit 3 of Address 00h with the same

logic levels as for Bit 7, Bit 6, and Bit 5 (bit pattern: XY1001YX

binary) allows the user to reprogram a lost serial port config-

uration and to reset the registers to their default values. A

second write to Address 00h with reset bit low and serial port

configuration as previously specified (XY) reprograms the OSC

IN multiplier setting. A changed fSYSCLK frequency is stable after

a maximum of 200 fMCLK cycles (equals wake-up time).

DAC OPERATION

The dual 12-bit DAC output of the AD9773, along with the

reference circuitry, gain, and offset registers, is shown in Figure 37

and Figure 38. Note that an external reference can be used by

simply overdriving the internal reference with the external

reference. Referring to the transfer functions in Equation 1, a

reference current is set by the internal 1.2 V reference, the

external RSET resistor, and the values in the coarse gain register.

The fine gain DAC subtracts a small amount from this and the

result is input to IDAC and QDAC, where it is scaled by an

amount equal to 1024/24. Figure 39 and Figure 40 show the

scaling effect of the coarse and fine adjust DACs. IDAC and

QDAC are PMOS current source arrays, segmented in a 5-4-3

configuration. The five most significant bits control an array of

31 current sources. The next four bits consist of 15 current

sources whose values are all equal to 1/16 of an MSB current

source. The three LSBs are binary weighted fractions of the

middle bits’ current sources. All current sources are switched to

either IOUTA or IOUTB, depending on the input code.

The fine adjustment of the gain of each channel allows for

improved balance of QAM modulated signals, resulting in

improved modulation accuracy and image rejection. In the

Interfacing the AD9773 with the AD8345 Quadrature

Modulator section, the performance data shows to what degree

image rejection can be improved when the AD9773 is used with

an AD8345 quadrature modulator from Analog Devices Inc.

FINE

GAIN

DAC

FINE

GAIN

DAC

COARSE

GAIN

DAC

COARSE

GAIN

DAC

OFFSET

DAC

OFFSET

DAC

GAIN

CONTROL

REGISTERS

OFFSET

CONTROL

REGISTERS

GAIN

CONTROL

REGISTERS

OFFSET

CONTROL

REGISTERS

1.2VREF

IDAC

QDAC

REFIO

0.1

μF

FSADJ1

RSET1

IOUTA1

IOUTA2

IOUTB1

IOUTB2

RSET2

FSADJ2

Figure 37. DAC Outputs, Reference Current Scaling,

and Gain/Offset Adjust

μA

0.7V

REFIO

AVDD

Figure 38. Internal Reference Equivalent Circuit

2R MODE

1R MODE

COARSE GAIN REGISTER CODE

(ASSUMING RSET1, RSET2 = 1.9kΩ)

010

Figure 39. Coarse Gain Effect on IFULLSCALE

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