AD9773-EB datasheet(29/60 Pages) AD

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AD9773

Rev. D | Page 29 of 60

Figure 48. PLL_LOCK Output Signal (Pin 8) in the

Process of Locking (Typical Lock Time)

It is important to note that the resistor/capacitor needed for the

PLL loop filter is internal on the AD9773. This suffices unless the

input data rate is below 10 MHz, in which case an external series

RC is required between the LPF and CLKVDD pins.

POWER DISSIPATION

The AD9773 has three voltage supplies: DVDD, AVDD, and

CLKVDD. Figure 49, Figure 50, and Figure 51 show the current

required from each of these supplies when each is set to the

3.3 V nominal specified for the AD9773. Power dissipation (PD)

can easily be extracted by multiplying the given curves by 3.3.

As Figure 49 shows, IDVDD is very dependent on the input data

rate, the interpolation rate, and the activation of the internal

digital modulator. IDVDD, however, is relatively insensitive to the

modulation rate by itself. In Figure 50, IAVDD shows the same

type of sensitivity to the data, the interpolation rate, and the

modulator function but to a much lesser degree (<10%). In

Figure 51, ICLKVDD varies over a wide range yet is responsible for

only a small percentage of the overall AD9773 supply current

requirements.

100

150

200

250

300

350

400

fDATA (MHz)

100

150

200

×, (MOD. ON)

Figure 49. IDVDD vs. fDATA vs. Interpolation Rate, PLL Disabled

×, (MOD. ON)

72.0

72.5

73.0

73.5

74.0

74.5

75.0

75.5

76.0

fDATA (MHz)

100

150

200

×, (MOD. ON)

Figure 50. IAVDD vs. fDATA vs. Interpolation Rate, PLL Disabled

fDATA (MHz)

100

150

200

Figure 51. ICLKVDD vs. fDATA vs. Interpolation Rate, PLL Disabled

SLEEP/POWER-DOWN MODES

(Control Register 00h, Bit 3 and Bit 4)

The AD9773 provides two methods for programmable

reduction in power savings. The sleep mode, when activated,

turns off the DAC output currents but the rest of the chip

remains functioning. When coming out of sleep mode, the

AD9773 immediately returns to full operation. Power-down

mode, on the other hand, turns off all analog and digital

circuitry in the AD9773 except for the SPI port. When

returning from power-down mode, enough clock cycles must

be allowed to flush the digital filters of random data acquired

during the power-down cycle.

AD9773-EB Datasheet(PDF) 29 Page - Analog Devices

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