M24128-DF datasheet(29/40 Pages) STMICROELECTRONICS

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M24128-BW M24128-BR M24128-BF M24128-DF

DC and AC parameters

Table 17. 400 kHz AC characteristics

Symbol

Alt.

Parameter

Min.

Max.

Unit

fSCL

Clock frequency

400

kHz

tCHCL

tHIGH

Clock pulse width high

600

tCLCH

tLOW

Clock pulse width low

1300

tQL1QL2(1)

1. Characterized only, not tested in production.

SDA (out) fall time

20(2)

2. With CL = 10 pF.

300

tXH1XH2

Input signal rise time

(3)

3. There is no min. or max. values for the input signal rise and fall times. It is however

recommended by the I²C specification that the input signal rise and fall times be more than

20 ns and less than 300 ns when fC < 400 kHz.

(3)

tXL1XL2

Input signal fall time

(3)

tDXCH

tSU:DAT Data in set up time

100

tCLDX

tHD:DAT Data in hold time

tCLQX(4)

4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and

the falling or rising edge of SDA.

tDH

Data out hold time

100(5)

5. 200 ns for previous devices identified by process letter A.

-ns

tCLQV(6)

6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either

0.3VCC or 0.7VCC, assuming that Rbus × Cbus time constant is within the values specified in

Figure 12.

tAA

Clock low to next data valid (access time)

900

tCHDL

tSU:STA Start condition setup time

600

tDLCL

tHD:STA Start condition hold time

600

tCHDH

tSU:STO Stop condition set up time

600

tDHDL

tBUF

Time between Stop condition and next Start

condition

1300

tWLDL(7)(1)

7. WC=0 set up time condition to enable the execution of a WRITE command.

tSU:WC WC set up time (before the Start condition)

µs

tDHWH(8)(1)

8. WC=0 hold time condition to enable the execution of a WRITE command.

tHD:WC WC hold time (after the Stop condition)

µs

tWR

Internal Write cycle duration

tNS(1)

Pulse width ignored (input filter on SCL and

SDA) - single glitch

-80(9)

9. 100 ns for previous devices identified by process letter A.

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