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AD9523 Datasheet(PDF) 11 Page - Analog Devices

Part # AD9523
Description  Jitter Cleaner and Clock Generator with 14 Differential or 29 LVCMOS Outputs
PDF  60 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9523 Datasheet(HTML) 11 Page - Analog Devices

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Data Sheet
AD9523
Rev. C | Page 11 of 60
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SCL, SDA Fall Time, tFALL
20 + 0.1 CB1
300
ns
Data Setup Time, tSET;DAT
100
ns
Data Hold Time, tHLD;DAT
100
880
ns
This is a minor deviation from the original I²C
specification of 0 ns minimum2
Capacitive Load for Each Bus Line, CB1
400
pF
1
CB is the capacitance of one bus line in picofarads (pF).
2
According to the original I2C specification, an I2C master must also provide a minimum hold time of 300 ns for the SDA signal to bridge the undefined region of the SCL
falling edge.



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